Intel Pentium III - Miscellaneous Checklist for 370-Pin Socket Processors; Clock Signals; Miscellaneous Signals

8-4 Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
8.6 Miscellaneous Checklist for 370-Pin Socket
Processors
Host bus clocks are critical. Signal integrity and timing of these signals should be carefully evaluated and
simulated. It is strongly recommended that system bus clocks be routed on signal layers next to the
ground layer and do not traverse multiple signal layers. Please see Chapter 4 for details.
Table 8-4. Clock Signals
CPU Pin Pin Connection
BCLK
BCLK#/CLKREF
For single ended clocking connect BCLK to clock generator through 22 - 33 Ω
series resistor (OEM must simulate based on driver characteristics). Connect
BCLK# to a filtered 1.25 V supply.To reduce pin-to-pin skew, tie host clock
outputs together at the clock driver then route to both processors and chipset.
For differential clocking signals must be length matched from the receivers to a
resistive network, and from the network to the receiver. The resistive network
consists of a 33.2 Ω 1% series resistor on each line, and a 475 Ω resistor
between them. Lastly both lines are pulled down with a 63.4 Ω 1% resistor to
GND. See Chapter 4 for more details.
PICCLK
Must be connected from the clock generator to the PICCLK pin on the CPUs.
Voltage divider circuitry should yield 2.0 V (OEM must simulate based on driver
characteristics).
Table 8-5. Miscellaneous Signals
CPU Pin Pin Connection
BSEL0
For single ended clocking connect to clock generator ONLY.Pullupto3.3Vwith
a1KΩ resistor. NC on processor 0 and 1.
For differential clocking connect BSEL0 on CPU0 to BSEL0 on CPU1, pull up to
3.3Vwitha1KΩ resistor, connect to clock generator
BSEL1
For single ended clocking connect to clock generator ONLY.Pullupto3.3Vwith
a1KΩ resistor. NC on processor 0 and 1.
For differential clocking connect BSEL1 on CPU0 to BSEL1 on CPU1, pull up to
3.3Vwitha1KΩ resistor, connect to clock generator.
CPUPRES#
Tie to GND, leave it N/C, or could be connected to powergood logic to gate
system from powering on if no processor is present.
DETECT Leave unconnected or connect to Vss
KEY Connect to Vss.
NCHCTRL Pull up through 14 Ω to V
TT
.
THERMDN Thermal diode cathode. Connect to thermal sensor device.
THERMDP Thermal diode anode. Connect to thermal sensor device.
RTTCTRL 68 Ω 1% pull-down to GND.