Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 4-1
Clocking 4
4.1 General Clocking Considerations
The host bus clock signals are critical signals in a platform design. The signal integrity and timing of
these signals should be carefully evaluated and simulated. The following sections provide host clocking
recommendations for the two supported Intel
®
Pentium
®
III Processor with 512KB L2 Cache clocking
methodologies: single-ended clocking and differential clocking.
In general, the following layout recommendations should be followed for the host bus clocks:
• It is recommended that system bus clocks be routed on the signal layer next to the ground layer
(referenced to ground).
• It is strongly recommended that system bus clocks do not traverse multiple signal layers.
• System clock routing over power plane splits should be minimized.
• If necessary, grounded guard band traces can be routed next to clock traces to reduce crosstalk to
other signals.
Figure 4-1 shows the host bus clocking connections that must be made in a dual-processor system.
Detailed information regarding the routing, layout, and termination of the processor and chipset
connections can be found in Section 4.2 and Section 4.3. The debug port routing has special
requirements and are covered in Section 4.4.
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