Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 7-9
The first modification that must be made is to strap the clocking and chipset circuitry to operate at 133
MHz. This is done by pulling up the BSEL pins on these devices to 3.3V. The clock generator and chipset
will now always operate at 133 MHz and will no longer depend on the processor to drive the host bus
frequency to the BSEL pins at power. Please note, however, that 133 MHz capable processors are all
that can be used in the system once this modification is made.
The VTT_PWRGD routing must also be modified to allow for legacy clock driver support. Even though
the host bus clocking is being strapped to a set value, the processors still require VTT_PWRGD to do
VID determination. The VTT_PWRGD signal from the selected VR should be routed to the VTT_PWRGD
input on both processor sockets. By routing the VTT_PWRGD signal this way, the signal will be available
to both processor sockets if only one contains a processor.
Dynamic BSEL selection could be used in a legacy or single-ended clock driver system. A complex
circuit to delay power delivery to the clock drivers and chipsets is needed to allow for dynamic BSEL
operation. Intel will not be pursuing such a design recommendation.
7.10 PICCLK Voltage Change
The voltage level for the PICCLK signal has changed to 2.0 volts. This change may require adjustments
to the PICCLK generator or external circuitry added to current designs so they provide the correct
voltage ranges.
7.11 ITP Changes
The Intel
®
Pentium
®
III Processor with 512KB L2 Cache uses different signaling levels than AGTL+ only
processors. Because of this, the In-Target Probe (ITP) interposer used for AGTL+ only processors is not
compatible with the Intel
®
Pentium
®
III Processor with 512KB L2 Cache platform. A new interposer and
software are available for the Intel
®
Pentium
®
III Processor with 512KB L2 Cache platform. Please
consult your ITP vendor for details.
7.12 Logic Analyzer Interface
The Intel
®
Pentium
®
III Processor with 512KB L2 Cache uses the AGTL signalling scheme. Since the
voltage swings and thresholds are different in AGTL than AGTL+ only processor platforms, a new logic
analyzer interface is required. Please contact your logic analyzer vendor for a compatible logic analyzer
interface.
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