Intel Pentium III - Processor Host Bus Design; Initial Timing Analysis; General Topology and Layout Guidelines; Layout Rules for AGTL Signals

Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide iii
Contents
1 Design Guide Introduction..................................................................................1-1
1.1 Audience ............................................................................................................1-1
1.2 Related Documents............................................................................................1-1
1.3 Conventions and Terminology............................................................................1-2
1.4 State of the Data ................................................................................................1-3
2 General Design Considerations........................................................................2-1
2.1 Nominal Board Stackup......................................................................................2-1
2.2 Socket 370 Component Keepout .......................................................................2-2
3 Processor Host Bus Design ...............................................................................3-1
3.1 Initial Timing Analysis.........................................................................................3-1
3.2 General Topology and Layout Guidelines..........................................................3-2
3.3 Terminator-less T Topology ...............................................................................3-4
3.4 Wired-OR Signal Considerations .......................................................................3-5
3.5 Simulation Methodology.....................................................................................3-7
3.6 Trace Routing.....................................................................................................3-7
3.7 Layout Rules for AGTL Signals..........................................................................3-7
3.7.1 Ground Reference.............................................................................3-7
3.7.2 Reference Plane Splits......................................................................3-7
3.7.3 CPU Connector Breakout..................................................................3-7
3.7.4 Minimizing Crosstalk .........................................................................3-8
3.8 Layout Rules for Non-AGTL (CMOS) Signals....................................................3-8
3.9 Undershoot/Overshoot Requirements................................................................3-9
3.10 Debug Port Routing Guidelines..........................................................................3-9
3.10.1 Target System Implementation .........................................................3-9
4 Clocking......................................................................................................................4-1
4.1 General Clocking Considerations.......................................................................4-1
4.2 Single Ended Host Bus Clocking Routing ..........................................................4-2
4.2.1 CLKREF Filter Implementation..........................................................4-4
4.2.2 Single-Ended Clocking BSEL[1:0] Implementation ...........................4-5
4.3 Differential Host Bus Clocking Routing ..............................................................4-5
4.3.1 Differential Clocking Topology...........................................................4-6
4.3.2 Differential Clocking BSEL[1:0] Implementation................................4-7
4.4 Debug Port Host Clock Connection....................................................................4-7
4.5 Clock Driver Decoupling and Power Delivery.....................................................4-8
5Power...........................................................................................................................5-1
5.1 Terminology........................................................................................................5-1
5.2 Typical Power Delivery.......................................................................................5-1
5.3 Dual Processor Power Requirements ................................................................5-3
5.3.1 Voltage Tolerance .............................................................................5-3
5.3.2 Multiple Voltages ...............................................................................5-4
5.3.3 Voltage Sequencing ..........................................................................5-4
5.4 Meeting Power Requirements............................................................................5-4
5.4.1 Supplying Voltage .............................................................................5-4