iv Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
5.4.2 Decoupling Technology and Transient Response.............................5-5
5.5 Recommendations .............................................................................................5-6
5.5.1 Decoupling Guidelines ......................................................................5-7
5.5.2 Processor PLL Filter Recommendations...........................................5-8
6 Thermals.....................................................................................................................6-1
6.1 THERMTRIP# Requirements.............................................................................6-1
6.2 THERMTRIP# Erratum ......................................................................................6-1
7 Processor Migration Considerations..............................................................7-1
7.1 Overview ............................................................................................................7-1
7.2 Implement VRM 8.5 ...........................................................................................7-1
7.2.1 VRM 8.5 Voltage Range....................................................................7-1
7.2.2 Active Voltage Positioning.................................................................7-2
7.2.3 VRM 8.5 Modules..............................................................................7-3
7.3 Package Changes (FC-PGA2)...........................................................................7-3
7.4 Pinout Changes..................................................................................................7-4
7.5 Dual Processor Specific Pin Recommendations................................................7-6
7.5.1 DETECT (AF36)................................................................................7-6
7.5.2 RESET2 (AJ3)...................................................................................7-6
7.5.3 KEY (AM2) ........................................................................................7-6
7.6 AGTL Bus Transition..........................................................................................7-6
7.7 Host Bus Layout Changes .................................................................................7-7
7.8 Single Ended Clocking Support .........................................................................7-7
7.9 VID & BSEL Signals...........................................................................................7-7
7.9.1 Power On Sequence .........................................................................7-8
7.9.2 Signalling Changes ...........................................................................7-8
7.9.3 Legacy Clock Driver Support.............................................................7-8
7.10 PICCLK Voltage Change ...................................................................................7-9
7.11 ITP Changes ......................................................................................................7-9
7.12 Logic Analyzer Interface.....................................................................................7-9
8 System Design Checklist.....................................................................................8-1
8.1 Introduction ........................................................................................................8-1
8.2 Design Checklist Summary................................................................................8-1
8.3 Host Interface AGTL Bus and AGTL Signals.....................................................8-1
8.4 CMOS (Non-AGTL) Signals...............................................................................8-2
8.5 TAP/ITP Checklist for 370-Pin Socket Processors ............................................8-3
8.6 Miscellaneous Checklist for 370-Pin Socket Processors ...................................8-4
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