Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide v
Index of Figures
2-1 Sample Board Stackup.......................................................................................2-1
2-2 Socket 370 Component Keepout .......................................................................2-2
2-3 Socket 370 Volumetric Keepout.........................................................................2-3
3-1 System Bus T-Topology.....................................................................................3-3
3-2 Terminator-less System Bus T Topology ...........................................................3-4
3-3 Wired-OR Termination Topology........................................................................3-6
3-4 Simple Terminations.........................................................................................3-10
3-5 TCK Termination, DP System ..........................................................................3-11
3-6 PRDYx# Signal Termination.............................................................................3-12
3-7 RESET# Signal Termination ............................................................................3-12
3-8 JTAG Signals TDI/TDO for Processor Only .....................................................3-14
3-9 TDO 3-Pin Jumper Bypass...............................................................................3-15
3-10 4-Pin Jumper Bypass .......................................................................................3-15
4-1 Host Bus Clock Connections..............................................................................4-2
4-2 Single Ended Clocking Topology - CPU.............................................................4-3
4-3 Single Ended Clocking Topology - Chipset........................................................4-3
4-4 CLKREF Filter Implementation...........................................................................4-4
4-5 Single Ended Clock BSEL Circuit.......................................................................4-5
4-6 Differential Clocking Topology............................................................................4-6
4-7 Differential Clock BSEL Circuit...........................................................................4-7
4-8 Debug Port Differential Host Clock Implementation...........................................4-8
5-1 Ideal Processor Power Supply Scheme.............................................................5-2
5-2 Power Distribution for a DP System Motherboard..............................................5-2
5-3 Detailed Power Distribution Model for System with VRM...................................5-3
5-4 VRM 8.5 Board Power Distribution Model..........................................................5-3
5-5 1206 Capacitor Pad and Via Layouts.................................................................5-5
5-6 PGA370 Decoupling Capacitor Placement ........................................................5-7
5-7 Processor PLL Filter...........................................................................................5-8
5-8 PLL Power Low Pass Filter Response...............................................................5-9
6-1 Example Dual Processor THERMTRIP# Workaround Circuit............................6-2
7-1 Voltage Range Comparison ...............................................................................7-2
7-2 Active Voltage Positioning Operating Parameters .............................................7-3
7-3 Package Comparisons .......................................................................................7-4
7-4 Electrical Keying Mechanism .............................................................................7-5
7-5 SE Clocking Implementation ..............................................................................7-8
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