vi Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
Index of Tables
3-1 System Timing Equations ..................................................................................3-1
3-2 System Timing Terms ........................................................................................3-1
3-3 System Bus Timing Parameters.........................................................................3-2
3-4 Sample CPU to CPU flight time calculations......................................................3-2
3-5 Trace Lengths for T Topology (ServerWorks Chipset).......................................3-3
3-6 Component Values for T Topology ....................................................................3-3
3-7 Trace Lengths for Terminator-less T Topology (ServerWorks Chipset).............3-5
3-8 Component Values for Terminator-less T Topology ..........................................3-5
3-9 Wired-OR Values ...............................................................................................3-6
3-10 System Signal Layout Guidelines ....................................................................3-10
3-11 JTAG Signal Layout Guidelines .......................................................................3-11
3-12 Execution Signals Routing Guidelines .............................................................3-11
3-13 Debug Port Termination Requirement .............................................................3-13
3-14 Routing Guidelines...........................................................................................3-13
4-1 Component Values for SE Clocking Topology - CPU ........................................4-3
4-2 Component Values for SE Clocking Topology - Chipset....................................4-4
4-3 CLKREF Component Values .............................................................................4-5
4-4 Component Values for Differential Clocking ......................................................4-6
5-1 Bulk Capacitance Recommendations ................................................................5-6
5-2 Vcc
CORE
High Frequency Capacitance Recommendations...............................5-7
6-1 THERMTRIP# Timing Requirements.................................................................6-1
7-1 Pin Differences List ............................................................................................7-4
7-2 Signalling Parameter Comparisons....................................................................7-6
8-1 AGTL Signals.....................................................................................................8-1
8-2 CMOS Signals....................................................................................................8-2
8-3 TAP/ITP Signals.................................................................................................8-3
8-4 Clock Signals .....................................................................................................8-4
8-5 Miscellaneous Signals........................................................................................8-4
8-6 Power Signals ....................................................................................................8-5