13
Half Step Mode
In half step mode the phasing alternates from one phase energized to two
phases energized. Half step mode is selected by a logic LOW on the Half/
Full step input.
Timing
Figure 1.2.5: Timing
Figure 1.2.3: Wave Mode Phase Sequence
1
35
7
2
4
6
8
2
46
82
46
82
STEP CLOCK
PHASE A
PHASE B
PHASE A
PHASE B
Figure 1.2.4: Half Step Mode
1
3
5
7
2
4
6
8
1
23
45
67
81
STEP CLOCK
PHASE A
PHASE B
PHASE A
PHASE B
t
CLK
t
S
t
H
STEP CLOCK
CW/CCW
HALF/FULL STEP
Parameter Minimum
t - Clock Time.......................3µs
t - Set up time...........................2µs
t - Hold Time..............................5.5µs
CLCK
S
H