E8257D/67D, E8663D PSG Signal Generators Service Guide
Troubleshooting
Overall Description
1-86
Option 1EH (reduced harmonics below 3.2 GHz) adds a filter assembly (A38 Low Band Switch Filter) after the
A8 Output. If Option UNW is installed, 1EH is installed after the A8 Output and before the UNW assembly.
The 100 kHz to 3.2 GHz signal is routed to the A23 Lowband Coupler/Detector, and then switched into the highband
path by a switch in the A30 Modulation Filter microcircuit. From this point, the low frequency signals flow to the
front panel through the highband path.
NOTE The following paragraph applies to E8257D instruments with Option 1EU and all E8663D instruments.
The A43 Amp Filter assembly is added to the low band RF path. The RF signal flow goes from the A8 Output board
into the A43 Amp FIlter and then into the A23 Low Band Coupler. The A43 Amp Filter induces the circuitry for
Options UNU and UNW for frequencies from 250 MHz to 3.2 GHz, Option 1EH, Option 007, Option 1EU, and a divider
circuitry used with Option UNX.
Frequency Control
CW Mode
The A9 YIG Driver, A18 CPU, A7 Reference, A5 Sampler, and A6 Frac–N establish frequency accuracy and stability.
This circuitry is commonly referred to as a phase lock loop (PLL).
In CW operation, the A18 CPU programs the A9 YIG Driver pre–tune DAC to output a voltage that coarsely tunes the
YIG oscillator to the desired frequency. The A18 CPU also sets the A6 Frac–N VCO and the A5 Sampler phase dividers
and VCO to a frequencies such that when the A6 Frac–N, A5 Sampler signal, and the YIG oscillator signals are in
phase, the output of the phase comparator is 0 volts, and the phase lock loop is at the desired output frequency.
When the phases of these two signals (YO feedback and reference) are not the same (in phase), the output of the
phase detector changes to some voltage other than 0 volts.
The phase detector output is then integrated (the integrator voltage is proportional to the frequency error), and
routed to the A9 YIG Driver where it is summed with the pre–tune DAC voltage, causing the YIG’s output frequency
to change. Once the phase of the two signals matches, the phase detector output voltage returns to 0 volts, and the
integrator maintains a constant output voltage, holding the YIG output frequency constant.
To perform a phase comparison between the A6 Reference signal and the RF signal coupled off by the A20 Doubler, a
sampling function on the A5 Sampler converts the RF (in GHz) to an IF frequency in the MHz range. A 10 MHz signal
from the A7 Reference Assembly is used as the reference to the A6 Frac–N VCO (Voltage Controlled Oscillator) to
maintain the A6 Frac–N frequency accuracy. The frequency reference for the A7 Reference can be an:
• external 10 MHz signal
• internal standard 10 MHz OCXO (Oven Controlled Crystal Oscillator) on the A7 Reference
• optional high–stability 10 MHz OCXO
In summary:
• The A18 CPU coarse tunes the YIG, and sets the A5 Sampler VCO frequency and the A6 Frac–N VCO frequencies.
• The A5 Sampler and A6 Frac–N VCO frequencies are not fixed, and vary according to the YIG frequency.
• In some modes, the A6 Frac–N’s VCO is divided on the A5 Sampler.
• The A5 Sampler converts the RF signal to an IF signal for phase comparison.
• After a phase detector determines the phase difference between the two signals, the phase detector output is
integrated. The integrated voltage is summed with the A9 YIG Driver pre–tune DAC voltage, causing the YIG
oscillator output frequency to change to the desired frequency.
Ramp Sweep Mode (Option 007)
The A9 YIG Driver, A18 CPU, A7 Reference and the A6 Frac–N are used in sweep mode, but the A5 Sampler is not.
The A9 YIG Driver does the following:
• generates the sweep rate
• sets the start frequency
• generates the sweep ramp
• provides delay compensation
• adjusts the ALC leveling reference for improved power flatness during sweep
The A6 Frac–N contains the phase lock circuitry required to monitor and maintain phase lock during sweep. It also
provides a correction frequency voltage to the A9 YIG Driver.
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