E8257D/67D, E8663D PSG Signal Generators Service Guide
Troubleshooting
Reference/Synthesis Loop Description
1-94
The speed at which the output of the Sweep DAC changes determines the instrument's sweep rate. The rate of change
is controlled by the output frequency of a digitally developed synthesis (DDS) chip on the A9 YIG Driver. The
A18 CPU sets the DDS output to a frequency between 0 and 25 MHz, and the DDS output frequency clocks a
programmable counter that drives the Sweep DAC rate of change. A low DDS frequency produces a slow sweep rate;
a high DDS frequency produces a high sweep rate.
In ramp sweep mode, the A9 YIG Driver Pre–tune DAC is set to 0V. Delay compensation is added to improve linearity,
and a fine tune correction from the A6 Frac–N is summed with the Sweep DAC voltage to maintain phase lock. The
phase lock correction voltage is generated on the A6 Frac–N by coupling off some of the YIG output frequency in the
A29 20 GHz Doubler, and routing it to the A6 Frac–N. On the A6 Frac–N, fixed and programmable dividers (controlled
by the A18 CPU) divide the RF signal down to 5 MHz.
Also on the A6 Frac–N, 10 MHz from the A7 Reference is divided down to 5 MHz. The phase of the two 5 MHz signals
is compared and integrated. The integrator’s output is routed to the A9 YIG Driver and summed with the Sweep DAC
(YIG Drive) voltage to maintain phase lock during sweep.
After the A18 CPU has everything set up, the A9 YIG Driver programmable counter is enabled and sweep begins. The
A6 Frac–N divide numbers determine how far the A6 Frac–N sweeps before the A18 CPU calculates new divide
numbers. The A6 Frac–N divide numbers are updated at filter switch points and at band crossings. During multiple
band sweeps, the A9 YIG Driver Sweep DAC, DDS, and delay compensation are updated at band crossings.
A5 Sampler (CW mode only)
The A5 Sampler contains a microwave sampler used to convert a portion of the YIG oscillator output frequency to an
IF frequency for phase comparison.
The A5 Sampler VCO provides the LO input to the sampler and the YIG oscillator provides the RF input. The VCO is
phase locked to the 1 GHz reference board output. The 1 GHz signal is split into 2 paths. One path is divided by 4
and mixed with the other path to generate a 750 MHz signal. The 750 MHz signal is then split into 2 paths, one of
which is divided down and input to a phase detector. The other path goes through a low pass filter and becomes the
LO side of the mixer. The RF side of the mixer is the sampler VCO output. The mixer IF output then passes through
a 155 MHz low pass filter and into the sampler phase detector. If the divided down 750 MHz path and the mixer
output do not agree, a sampler lock is reported.
The A5 VCO output frequency (LO input) is set between 618 and 905 MHz, the RF input is between 3.2 and 10 GHz
and the sampler output is an IF signal between 30 and 64 MHz. The IF signal passes through an 80 MHz low pass
filter, eliminating all signals above 80 MHz that might pass through the sampler.
The IF signal is one input to a phase comparator. The second input to the phase comparator is 10 to 80 MHz, and is
the result of dividing or mixing the 500 to 1000 MHz signal from the A6 Frac–N VCO. The output of the phase
comparator is a voltage proportional to the difference in phase that is integrated and summed with the pre–tune
voltage on the A9 YIG Driver, fine tuning the YIG oscillator to the desired frequency.
The sampler contributes to the phase noise at offsets between 10 KHz and 100 KHz. Phase noise is better in FM off
mode than in FM on mode. In off mode the A6 Frac–N VCO signal on the A5 Sampler is divided down to get the
phase comparator reference frequency of 10 and 80 MHz. In FM on mode, and for FM rates above 230 Hz, phase noise
performance degrades because the A6 Frac–N VCO uses a mixer (required for higher FM rates) to get to the reference
frequency.
A6 Frac–N
CW Mode
The A6 Frac–N uses a dividing technique to set the YIG Oscillator to the desired frequency. Because the A6 Frac–N
VCO output is the phase reference for the comparator on the A5 Sampler, small changes in the Frac–N programmable
divider number result in small changes in the A6 Frac–N VCO output frequency, which result in small changes in the
YIG Oscillator frequency.
The A6 Frac–N can contribute to phase noise between 5 and 10 KHz. This overlaps with the frequencies over which
the A7 Reference contributes to phase noise. There is no easy way to identify if a phase noise problem in the
overlapping area is generated by the A6 Frac–N or A7 Reference, other than to try new assemblies.
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