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ECP5 and ECP5-5G High-Speed I/O Interface
• It is recommend that clock input be located on the same side as data pins
• The top side of the device does not have Edge clocks hence can only be used to receive lower speed interfaces
(<200 MHz) that use 1x gearing. Top side of the device can be used for single ended interfaces only.
• Interfaces using the x1 gearing will use the primary clock resource. You can use as many interfaces as the num-
ber of primary clocks supported in the device.
• In addition to dedicate PCLK pins, ECP5 and ECP5-5G devices have GR_PCLK pins, these use shortest general
route path to get to the primary clock tree. These pins are not recommended for use with DDR interfaces. They
can be used for SDR or other generic FPGA designs.
Transmit interface Guidelines
• Use PADA and PADB for all TX using true LVDS interfaces.
• When implementing Transmit Centered interface, two ECLKs are required. Once to generate the Data Output
and the other to generate the CLK Output.
• When implementing Transmit Aligned interface only one ECLK is required for both Data output and Clock output.
• Each side has two CLKDIV modules which would mean you can implement two different GDDRX2 TX interface
per side since each 2X gearing would require CLKDIV module to generate a slower SCLK.
• The top side of the device does not have Edge clocks hence can only be used to receive lower speed interfaces
(<200 MHz) that use 1x gearing. Top side of the device can be used for single ended interfaces only.
• Interfaces using the x1 gearing will use the primary clock resource. You can use as many interfaces as the num-
ber of primary clocks supported in the device.
Clocking Guidelines for Generic DDR Interface
• The edge clock and primary clock resources are used when implementing a 2X receive or transmit interface.
• Only the primary clock (PCLK) resources are used when implementing x1 receive or transmit interfaces.
• Each edge clock can only span up to one side (Left or Right) of the device, hence all the data bits of the in the x2
interface must be locked to one side of the device. If wide bus implementation is required then the ECLKBRIDGE
element must be used to bridge the edge clock to the other side. ECLKBRIDGE can be used to bridge the Left
and Right Side ECLKs.
• When implementing x1 interfaces, the bus can span Left, Right or Top sides as primary clocks can access DDR
registers on all sides.
• Bottom side only supports SERDES function hence does not have any edge clocks or DDR registers except on
the LFE-85 device, some I/Os support 1X DDR registers similar to the Top side.
• The ECLK to DDR registers can be accessed through dedicated PCLK pins, GPLL outputs, DDRDLL outputs.
See TN1263, ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide for details.
• Primary clock to DDR registers can be accessed through dedicated PCLK pins, GPLL outputs and CLKDIV out-
puts. See TN1263, ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide for details.
• None of the clocks going to the DDR registers can come from internal general routing.
• DQS clocking is used for DDR memory interface implementation. DQS clock spans every 12 to 16 I/O’s include
the DQS pins. Refer to the “DQ-DQS Grouping” section for pinout assignment rules when using DQS clocking.
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