Lattice Semiconductor ECP5 Technical Notes

70
ECP5 and ECP5-5G High-Speed I/O Interface
Memory Output DDR Primitives for DQ Outputs
The following are the primitives used to implement various memory DDR output configurations to generate the DQ
outputs.
ODDRX2DQA
This primitive is used to generate DQ data output for DDR2 with x2 gearing and for DDR3 memory interface.
Figure 63. ODDRX2DQA
Table 33. ODDRX2DQA Port List
Memory Output DDR Primitives for DQS Output
Following are the primitives used to implement the DQS outputs to the DDR memory.
ODDRX2DQSB
This primitive is used to generate DQS clock output for DDR2 and DDR3 memory.
Figure 64. ODDRX2DQSB Primitive
Port I/O Description
D0, D1, D2, D3 I Data input to the ODDR (D0 is output first, D3 last)
ECLK I Fast edge clock input
DQSW270 I Clock that is 90° ahead of clock used to generate the DQS output
SCLK I SCLK input
RST I Reset input
Q O DDR data output on both edges of DQSW270
D0
D1
SCLK
RST
Q
ODDRX2DQA
D2
D3
ECLK
DQSW270
D0
D1
SCLK
RST
Q
ODDRX2DQSB
D2
D3
ECLK
DQSW

Lattice Semiconductor ECP5 Specifications

General

Brand	Lattice Semiconductor
Model	ECP5
Category	Recording Equipment
Language	English