EasyManuals Logo

Lattice Semiconductor ECP5 Technical Notes

Default Icon
78 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #57 background imageLoading...
Page #57 background image
57
ECP5 and ECP5-5G High-Speed I/O Interface
Table 13. DDR_MEM Advanced Settings Tab Parameters
Building DDR Interfaces in Clarity Designer
After all the DDR Modules are configured, they can be connected up together in the Builder Tab of Clarity Designer.
The connections made in the “Builder” will be carried over to the combined HDL file that will contain all the DDR
module instances. If the DDR modules were to share resources, the connections for the sharing can be done here.
For example, if a single PLL was shared among the different modules, then the clocks can be connected together
in the Builder Tab.
For step by step instructions on using the “Builder”, refer to the Clarity Designer User Manual.
Planning DDR Interfaces in Clarity Designer
Once the interface are configured and connected, the placement of these modules can be planned in the “Planner”
tab of Clarity Designer.
The Planner will allow user to drag & drop each DDR interface into the Chip View. This will automatically lock the
pins for that DDR interface at the selected location. The planner takes into account all the clocking & placement
requirements, any architecture limitations for each type DDR interface. If any of the placement rules are violated
the planner will not place the module if there aren’t enough resources or it will place it at the next available location.
This capability allows user to plan and place all the DDR interfaces before Synthesis. The placement constraints
will be carried over through the rest of the flow. Since all the design constraints are taken into account it saves the
user a lot of time to not have to run multiple iterations through the tool.
For step by step instructions on using the Planner, refer to the Clarity Designer User Manual.
Figure 50 shows DDR modules that are placed using Clarity Design Planner.
GUI Option Range Default Value
DQS Read Delay Adjustment FACTORYONLY, PLUS, MINUS FACTORYONLY
DQS Read Delay Value Grey out (if DQS Delay Adjustment = FACTORY-
ONLY)
0-255 (if DQS delay adjustment = PLUS)
1-256 (If DQS delay Adjustment = MINUS)
DQS Write Delay Adjustment FACTORYONLY, PLUS, MINUS FACTORYONLY
DQS Write Delay Value Grey out (if DQS Delay Adjustment = FACTORY-
ONLY)
0-255 (if DQS delay adjustment = PLUS)
1-256 (If DQS delay Adjustment = MINUS)

Table of Contents

Other manuals for Lattice Semiconductor ECP5

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Lattice Semiconductor ECP5 and is the answer not in the manual?

Lattice Semiconductor ECP5 Specifications

General IconGeneral
BrandLattice Semiconductor
ModelECP5
CategoryRecording Equipment
LanguageEnglish

Related product manuals