Lattice Semiconductor ECP5 Technical Notes

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ECP5 and ECP5-5G High-Speed I/O Interface
Figure 45. GDDR_7:1 LVDS Configuration Tab
Table 10 explains the various parameters in this tab.
Table 10. GDDR_7:1 LVDS Configuration Parameters
Configuring DDR Memory Interfaces
Clarity Designer is used to configure the PHY portion of the DDR2, DDR3, DDR3L, LPDDR2 and LPDDR3 mem-
ory interfaces. For the detailed block diagram for each interface, see the Memory Interface Implementation section.
To build a DDR Memory interface, select DDR_MEM option under Architecture Modules – IO in the Catalog Tab of
Clarity Designer. Enter the name of the module.
Figure 46 shows the type of interface selected as “GDDR_MEM” and module name entered. This module can then
be configured by clicking the Customize button.
GUI Option Description Values
Interface Type Type of interface (Receive or Transmit) Transmit, Receive
Bus Width Bus width for 1 channel of 7:1 LVDS interface 1 – 16
Clock Frequency Pixel clock speed 3.125 MHz – 108 MHz
Enable Bit Alignment & Word Align-
ment
Soft IP included with the module to implement Bit and
Word alignment for the parallel data on the 7:1 LVDS
Receive Interface
Enable, Disable

Lattice Semiconductor ECP5 Specifications

General

Brand	Lattice Semiconductor
Model	ECP5
Category	Recording Equipment
Language	English