74
ECP5 and ECP5-5G High-Speed I/O Interface
Detailed Description of Each Soft IP
GDDR_SYNC
This module is needed to startup al RX Centered and all TX interfaces with 2x gearing.
Figure 68. GDDR_SYNC Ports
Table 40. GDDR_SYNC Port List description
RX_SYNC
This module is needed to startup RX Aligned interfaces with 2x gearing.
Figure 69. RX_SYNC Ports
Port In/Out Descriptions
SYNC_CLK IN Startup clock. This cannot be the RX_CLK or divided version. It can be other low
speed continuously running clock. For example, oscillator clock
RST IN Active high reset to this sync circuit. When RST=1,
STOP=0, DDR_RESET=1, READY=0
START IN Start sync process. This is used to wait for PLL lock, then start sync process in
7:1 LVDS interface
STOP OUT Connects to ECLKSYNC.STOP
DDR_RESET OUT Reset to all IDDRX or ODDRX components and CLKDIV
READY OUT Indicate that startup is finished and RX circuit is ready to operate
GDDR_SYNC
RST
START
SYNC_CLK
DDR_ RESET
STOP
READY
STOP
DLL_LOCK
FREEZE
UDDCNTLN
DLL_RESET
DDR_RESET
SYNC_CLK
RST
UPDATE
READY
RX_SYNC
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