75
ECP5 and ECP5-5G High-Speed I/O Interface
Table 41. RX_SYNC Port Description
MEM_SYNC
This module is needed to startup external memory controller interfaces with 2x gearing.
Figure 70. MEM_SYNC Ports
Table 42. MEM_SYNC Port Description
Port In/Out Descriptions
SYNC_CLK IN Startup clock. This cannot be the RX_CLK or divided version. It can be other low
speed continuously running clock. For example, oscillator clock.
RST IN Active high reset to this sync circuit. When RST=1,
STOP=0, FREEZE=0, UDDCNTLN=1,
DLL_RESET=1, DDR_RESET=1, READY=0.
DLL_LOCK IN LOCK output from DDRDLL
UPDATE IN UPDATE can be used to re-start sync process. READY will go low and wait for
sync process to finish before going high again. This can only be performed when
no traffic is present.
STOP OUT Connect to ECLKSYNC.STOP.
FREEZE OUT Connect to DDRDLL.FREEZE.
UDDCNTLN OUT Connect to DDRDLL.UDDCNTLN
DLL_RESET OUT Reset to DDRDLL
DDR_RESET OUT Reset to all IDDRX components and CLKDIV
READY OUT Indicate that startup is finished and RX circuit is ready to operate
Port In/Out Descriptions
START_CLK IN Startup clock. This cannot be the RX_CLK or divided version. It can be other low
speed continuously running clock. For example, oscillator clock.
RST IN Active high reset to this sync circuit. When RST=1,
STOP=0, FREEZE=0, UDDCNTLN=1,
DLL_REEST=1, DDR_RESET=1, READY=0
PAUSE =0.
DLL_LOCK IN LOCK output from DDRDLL
UPDATE IN After ready goes high, user can use UPDATE to update code in DQSBUF, per-
form training (change read_clk_sel) or write leveling (change dyndelay<>).
PAUSE OUT Connect to DQSBUF.PAUSE
STOP OUT Connect to ECLKSYNC.STOP.
FREEZE OUT Connect to DDRDLL.FREEZE.
UDDCNTLN OUT Connect to DDRDLL.UDDCNTLN
DLL_RESET OUT Reset to DDRDLL
DDR_RESET OUT Reset to all IDDRX, ODDRX, OSHX components, DQSBUF and CLKDIV
READY OUT Indicate that startup is finished and RX circuit is ready to operate
DLL_ LOCK
FREEZE
UDDCNTLN
DLL_RESET
DDR_RESET
STOP
START_ CLK
RST
UPDATE
PAUSE
READY
MEM_SYNC
To Next Page
Loading...
Need help?
General
