Lattice Semiconductor ECP5 Technical Notes

78
ECP5 and ECP5-5G High-Speed I/O Interface
Technical Support Assistance
Submit a technical support case via www.latticesemi.com/techsupport.
Revision History
Date Version Change Summary
November 2015 1.1 Added support for ECP5-5G.
Changed document title to ECP5 and ECP5-5G High-Speed I/O Inter-
face.
Updated the following figures:
— Figure 4, GDDRX1_RX.SCLK.Centered Interface (Static Delay)
— Figure 5, GDDRX1_RX.SCLK.Centered Interface (Dynamic Data
delay)
— Figure 6, GDDRX1_RX.SCLK.Aligned Interface (Static Delay)
— Figure 7, GDDRX1_RX.SCLK.Aligned Interface (Dynamic
Data/Clock Delay)
— Figure 8, GDDRX2_RX.ECLK.Centered Interface (Static Delay)
— Figure 9, GDDRX2_RX.ECLK.Centered Interface (Dynamic Data
delay)
— Figure 10, GDDRX2_RX.ECLK.Aligned Interface (Static Delay)
— Figure 11, GDDRX2_RX.ECLK.Aligned Interface (Dynamic
Data/Clock Delay)
— Figure 12, GDDRX2_RX.MIPI
— Figure 13, GDDRX71_RX.ECLK Interface
— Figure 15, GDDRX1_TX.SCLK.Centered Interface
— Figure 16, GDDRX2_TX.ECLK.Aligned Interface
— Figure 17, GDDRX2_TX.ECLK.Centered Interface
— Figure 18, GDDRX71_TX.ECLK.Centered Interface
— Figure 31, DDR2, DDR3/DDR3L, LPDDR2 and LPDDR3 Read side
Implementation
— Figure 39, SDR Option Selected in the Catalog Tab of Clarity
Designer
— Figure 41, DDR_Generic Option Selected in the Catalog Tab of Clar-
ity Designer
— Figure 44, Option Selected in the Catalog Tab of Clarity Designer
— Figure 46, DDR_MEM Option Selected in the Catalog Tab of Clarity
Designer
Updated Technical Support Assistance section.
March 2014 01.0 Initial Release

Lattice Semiconductor ECP5 Specifications

General

Brand	Lattice Semiconductor
Model	ECP5
Category	Recording Equipment
Language	English