Home
Lattice Semiconductor
Recording Equipment
ECP5
Lattice Semiconductor ECP5 Technical Notes
4
of 1
of 1 rating
78 pages
Give review
Manual
Specs
To Next Page
To Next Page
To Previous Page
To Previous Page
Loading...
50
ECP5 and ECP5-5G Hi
g
h-Speed I/O Interface
Figure 44. GDDR_7:1 Option Selec
ted in the Catalog T
ab of Clarity Designer
Clicking
Customize
displa
ys the Configuration T
ab where the 7:1
L
VDS interf
ace can be configured. Figure
45
shows the
“Configura
tion” tab f
or 7:1 L
VDS interf
aces.
49
51
Table of Contents
ECP5 and ECP5-5G High-Speed I/O Interface
1
Introduction
1
External Interface Description
1
High-Speed I/O Interface Building Blocks
2
Edge Clocks
2
Primary Clocks
2
DQS Lane
2
PLL
3
DDRDLL
3
DQSBUF
3
DLLDEL
3
Input DDR (IDDR)
4
Output DDR (ODDR)
4
Edge Clock Dividers (CLKDIV)
4
Input/Output DELAY
4
Building Generic High Speed Interfaces
5
Types of High-Speed DDR Interfaces
5
High-Speed DDR Interface Details
6
GDDRX1_RX.SCLK.Centered
6
GDDRX1_RX.SCLK.Aligned
7
GDDRX2_RX.ECLK.Centered
8
GDDRX2_RX.ECLK.Aligned
9
GDDRX2_RX.MIPI
11
GDDRX71_RX.ECLK
12
GDDRX1_TX.SCLK.Aligned
13
GDDRX1_TX.SCLK.Centered
14
GDDRX2_TX.ECLK.Aligned
15
GDDRX2_TX.ECLK.Centered
15
GDDRX71_TX.ECLK
16
Generic DDR Design Guidelines
17
Using the High Speed Edge Clock Bridge
17
Receive Interface Guidelines
17
Transmit interface Guidelines
18
Clocking Guidelines for Generic DDR Interface
18
Timing Analysis for High Speed DDR Interfaces
19
ECP5 and ECP5-5G Memory Interfaces
23
DDR Memory Interface Requirements
26
Features for Memory Interface Implementation
27
Memory Interface Implementation
32
DDR Memory Interface Design Rules and Guidelines
38
DDR2/DDR3 Memory Interface Termination Guidelines
39
DDR Memory Interface Pinout Guidelines
40
Pin Placement Considerations for Improved Noise Immunity
41
Using Clarity Designer to Build and Plan High Speed DDR Interfaces
42
Configuring DDR Modules in Clarity Designer
42
Configuring SDR Modules
43
Configuring DDR Generic modules
45
Configuring 7:1 LVDS Interface Modules
49
Configuring DDR Memory Interfaces
51
Building DDR Interfaces in Clarity Designer
57
Planning DDR Interfaces in Clarity Designer
57
DDR Software Primitives and Attributes
59
Input/Output DELAY
59
DELAYF
60
DELAYG
60
DELAY Attribute Description
61
DDRDLL (Master DLL)
61
DLL Delay (DLLDEL)
62
Generic DDR Input and Output Primitives
63
Input DDR Primitives
63
Output DDR Primitives
64
Memory DDR Primitives
66
Input and Output Memory DDR Primitives
68
Memory Input DDR Primitives
69
Memory Output DDR Primitives for DQ Outputs
70
Memory Output DDR Primitives for DQS Output
70
Memory Output DDR Primitives for Tristate Output Control
71
Memory Output DDR Primitives for Address and Command
72
Soft IP Modules
73
Detailed Description of Each Soft IP
74
Technical Support Assistance
78
Revision History
78
Other manuals for Lattice Semiconductor ECP5
User Guide
41 pages
Technical Note
86 pages
Quick Start Guide
15 pages
4
Based on 1 rating
Ask a question
Give review
Questions and Answers:
Need help?
Do you have a question about the Lattice Semiconductor ECP5 and is the answer not in the manual?
Ask a question
Lattice Semiconductor ECP5 Specifications
General
Brand
Lattice Semiconductor
Model
ECP5
Category
Recording Equipment
Language
English
Related product manuals
Lattice Semiconductor ECP5 Versa
32 pages
Lattice Semiconductor MIPI
31 pages
Need help?
General
To Next Page
