Lattice Semiconductor ECP5 - FPGA GPIO Pin Mapping

25
ECP5 and ECP5-5G High-Speed I/O Interface
Figure 25. Typical LPDDR2/LPDDR3 Memory Interface
Figure 26. DQ-DQS During Read
Figure 27. DQ-DQS During Write
DQS
(at PIN)
DQ
(at PIN)
DQS
(at IDDR)
DQ
(at IDDR)
90 degree phase shift between DQS pin to IDDR
Preamble
Postamble
DDR 1/ DDR 2
DDR 3
DQS
(at PIN)
DQ
(at PIN)
DQS
(at PIN)
DQ
(at PIN)