Lattice Semiconductor ECP5 Technical Notes

28
ECP5 and ECP5-5G High-Speed I/O Interface
In case of DDR2/DDR3/DDR3L, additional I/O pads are required to implement address, command and control.
They do not have to be I/Os in DQS groups but need to use 1X gearing generic output DDR capable pads.
Each of the dedicated DQS pins is internally connected to the DQS phase shift circuitry. The pin out sheets
included as part of DS1044, ECP5 and ECP5-5G Family Data Sheet shows pin locations for each of the DQS
groups.
DLL-Compensated DQS Delay Elements
The DQS to and from the memory is connected to the DQS delay element inside the ECP5 and ECP5-5G device.
The DQS delay block receives the delay control code, DDRDEL, from the on-chip DDRDLL. The code generated
by DDRDLL is connected to the DQSBUF circuit to perform 90° read phase shift and 90° write phase shift.
DDRDLL requires the frequency reference from PLL, normally going through the edge clock tree.
ECP5 and ECP5-5G devices support one DDRDLL modules in each corner of the device. The DQSBUF modules
that receive the DDRDEL code from DDRDLL can either receive the code from the top or bottom DDRDLL on that
side. Hence each side can support up to two different rate DDR memory interfaces.
Table 3. DDRDLL Connectivity
The DQS received from the memory is delayed in the DQS delay element in the DQSBUF block, and this delayed
DQS is used to clock the first set stage DDR input registers.
Figure 29. DQSBUF Block Functions
DDRDLL Location Left DQSBUFs Right DQSBUFs
DDRDLL_TR X
DDRDLL_TL X
DDRDLL_BR X
DDRDLL_BL X

Lattice Semiconductor ECP5 Specifications

General

Brand	Lattice Semiconductor
Model	ECP5
Category	Recording Equipment
Language	English