Lattice Semiconductor ECP5 - ECP5 Bank Pin Assignments

37
ECP5 and ECP5-5G High-Speed I/O Interface
Figure 36. LPDDR3 Output side for CA Generation
Figure 37. LPDDR3 Output side for CSN, CKE, ODT and CLOCK generation
DQSBUFM
‘0’
‘0’
wrloadn_cmd
wrmove_cmd
wrdirection_cmd
wrcflag_cmd
ca <n>_in(0)
Q
From Input side
DDRDLLA
CA[9:0]
‘0’
‘0’
‘0’
‘0’
‘0’
ca <n>_in(1)
ca <n>_in(2)
ca <n>_in(3)
‘0’
‘0’
Pause_CA
Pause output of
MEM_SYNC
D0
D1
RST
DQSW270
D2
D3
SCLK
ECLK
ODDRX2DQA
DQSI
DDRDEL
READ[1:0]
READCLKSEL0
READCLKSEL1
READCLKSEL2
RDLOADN
RDMOVE
RDDIRECTION
WRLOADN
WRMOVE
WRDIRECTION
DATAVALID
BURSTDET
RDCFLAG
WRCFLAG
DYNDELAY
[7:0]
PAUSE
SCLK
DQSW270
ECLK
DQSW
DQSR 90
WRPNTR[2:0]
RDPNTR[2:0]
DDR_reset
Sclk (from CLKDIVF as shown in the Input interface)
Eclk (from ECLKSYNCB as shown in the Input interface)
D0
D1
SCLK
RST
Q
1'b0
CLKP/
CLKN
DQSBUFM
DQSI
DQSR90
DDRDEL
READ[1:0]
WRPNTR[2:0]
RDPNTR[2:0]
SCLK
RST
READCLKSEL
0
READCLKSEL1
READCLKSEL2
DQSW270
RDLOADN
RDMOVE
RDDIRECTION
WRLOADN
WRMOVE
WRDIRECTION
DATAVALID
BURSTDET
RDCFLAG
WRCFLAG
ECLK
DYNDELAY[7:0]
D2
D3
ECLK
DQSW
1'b0
DQSW
PAUSE
From Input side
DDRDLLA
1'b1
1'b1
D0
D1
RST
DQSW
D2
D3
SCLK
ECLK
Q
csn,cke,
odt
csn/cke/
odt_in(0)
csn/cke/
odt_in(1)
‘0’
‘0’
‘0
‘0
‘0
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
DDR_reset
Sclk (from CLKDIVF as shown in the Input interface)
Eclk (from ECLKSYNCB as shown in the Input interface)
ODDRX2DQSB
ODDRX2DQSB