IESO = 1 in combination with either FCKSM = 0x11 or 0x01 should be exclusive of each other except in
very controlled conditions where the possibility of both NOT happening simultaneously can be guaranteed.
Problem 11: T
rying to clock switch from FRC to FRC w/PLL, but the system clock is still only 8 MHz and the
OSCCON.OSWEN bit indicates the clock switch never completed.
Note: Refer to the appropriate data sheet, but this is a typical OSCCON.NOSC clock source listing.
Software clock switching only supports switching between any of these combinations using the OSCCON clock
switch procedure:
OSCCON.NOSC: New Oscillator Selection bits
111 = Reserved
110 = Backup Fast RC (BFRC) Oscillator
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = USB PLL (UPLL) input clock and divider are set by UPLLCON
010 = Primary Oscillator (POSC) (HS or EC)
001 = System PLL (SPLL) input clock and divider set by SPLLCON
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits
There is an FRC and a separate SPLL, but no FRC_PLL. In order to do that, the user needs to follow these steps
assuming they are already running on an FRC and the users PLL configurations bits were not configured during
compile or programming step in anticipation of the FRC_PLL operation later for a future clock switch. If not, then the
user must perform these actions:
1. Configure PLL SPLLCON.PLLMULT, PLLODIV, and PLLRANGE. (i.e., SPLLCON.PLLIDIV is ignored when
PLLICLK = 1).
2. Write SPLLCON.PLLICLK to select FRC as input to the PLL.
3. Perform the OSCCON unlock sequence.
4. Write NOSC = SPLL and OSWEN = 1 to perform the OSCCON clock switch.
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MCU Start-up Problems
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DS70005439B-page 22
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