11.4.1 Key SD Host Controller (SDHC) Protection Design Points
• The SD card receptacle should be connected to the chassis AC earth ground if possible, or through a 100k
resistor to digital ground to attenuate any potential ESD discharge event.
•
Signal termination resistors in this case are not required, because the ESD protection device CM1422-03CP has
a 100 Ohm series resistor as part of the ESD RC filter.
• All SD card signals are routed through the ESD RC filter.
There is comprehensive information available on ESD, EMI, or EFT on the Microchip web site that can be found in
the document: AN2587 - EMI, EMC, EFT, and ESD Circuit Design Consideration for 32-bit Microcontrollers, or on any
of the 32-bit product web pages under the tab Documentation > Application Notes.
Return to Checklist
11.5 UART
Problem 32: Why is the UAR
T data corrupted?
• The UART baud rate error cannot exceed ±3% total by industry specification (i.e., ±1.5% Transmitter plus ±1.5%
Receiver allowance) between source and target. There are two sources of error in the MCU UART:
– The MCU UART clock source % accuracy error
– BRERR = (((BR
DESIRED
– MCU BR
CALCULATED
) / MCU BR
CALCULATED
) * 100%)
TOTAL MCU UART BAUD_RATE
ERROR
= (BR
ERR
% + UART clock source % error) ≤ 1.5%
If using an internal RC clock for the UART clock source, check the data sheet and confirm if the RC
plus PLL or DFLL has the required guaranteed % error accuracy
. In many MCU’s an external clock
reference like a crystal or clock oscillator are needed for the accuracy required.
• Unique to the PIC32MZ/PIC32MK family, REFCLK can also be selected as a UART clock source.
Never use REFCLK as a source clock for any asynchronous peripheral (i.e., UART, CAN, ADC,
and so on). REFCLK produces a pseudo fractional clock frequency by cycle stealing to produce
an average frequency
, meaning that over a given unit of time the number of clocks pulses are not
consistent. This means that the UART bit times cannot be guaranteed.
Problem 33: Why is the first UAR
T byte always wrong after a power-up or wake from sleep?
• On any reset the I/O pins are Tri-Stated and generally float low, remaining that way until the user’s code
initializes the UART and assigns the pins. For other UART devices in the application the High-Z floating logic low
condition is perceived as a “START” bit. The target UART Rx sees a false floating low start condition, and will
begin sampling the Rx pin data even if there is no actual transmitted data.
Always use pull up on the MCU UART Tx and Rx pins. The resulting MCU logic high on the Tx and
Rx logic in the system during the MCU reset and initialization period represents the UAR
T’s natural
idle state.
• On many MCU devices and in some sleep modes, the UART clocks are disabled and re-enabled on wake from
sleep by an interrupt triggered by the reception of a ST
ART bit (i.e., logic high-to-low transition). The falling edge
of the START bit is what synchronizes the sampling bit clock of the UART receiver. However, by the time the
MCU can wake from sleep and re-enable the clocks, the receiver bit sampling is no longer in phase with the
external transmitted Tx data.
Serial Data Corruption Errors
© 2022 Microchip T
echnology Inc.
and its subsidiaries
Manual
DS70005439B-page 41
To Next Page
Loading...
Need help?
General
