promote an efficient layout, because the active devices are unlikely to require two different voltages at any one
position on the board.
22.
The separation between any two power planes on a given layer should be at least 3 mm, (i.e., 11Kv isolation).
If two planes get too close to each other on the same layer, significant high-frequency coupling may occur.
Under adverse conditions, arcing or shorts may also be a problem if the planes are too closely spaced.
23. On a board with power and ground planes, no traces should be used to connect to power or ground.
Connections should be made using a via adjacent to the power or ground pad of the component. Traces on
a connection to a plane located on a different layer take up space and add inductance to the connection. If
high-frequency impedance is an issue (as it is with power bus decoupling connections), this inductance can
significantly degrade the performance of the connection.
24. If the design has more than one ground plane layer, then any connection to ground at a given position should
be made to all the ground layers at that position. The overall guiding principle here is that high-frequency
currents will take the most beneficial (lowest inductance) path if allowed to. Do not try to direct the flow of
these currents by only connecting to specific planes.
25. Ideally there should be no gaps or slots in the ground plane unless user has sensitive analog logic they are
attempting to isolate (refer to Analog Versus Digital Ground Layout Placement). It's usually best to have a solid
ground (signal return) plane and a layer devoted to this plane. Any additional power or signal current returns
that must be DC isolated from the ground plane should be routed on layers other than the layer devoted to the
ground plane.
26. Be certain to review the entire PCB design for any high-speed signal traces crossing over any reference plane
cuts. This will more than likely create an EMC occurrence. Avoid this.
27. All power or ground conductors on the board that contact (or couple to) the chassis, cables or other good
"antenna parts" must be bonded together at high frequencies. Unanticipated voltages between different
conductors both nominally called ground are a primary source of radiated emission and susceptibility
problems.
17.1 PCB Bypassing
1. Bypass capacitors must be placed near all power entry points on the PCB. These caps will keep unwanted
high-frequency noise from entering the design; the noise will simply be shunted to the ground.
2. Bypass capacitors must be utilized on all IC power supply connections and all voltage regulators in the design.
3. All bypass capacitor leads should be as short as possible. The best solutions are plane connection vias inside
the capacitor surface mount pads. When using vias outside the surface mount pads, pad-to-via connections
should be less than 5- 10 mils in length. Trace connections must be as wide as possible to lower inductance.
4. IC decoupling capacitors and ferrite beads should be placed as close to the IC power pins as possible. It
is recommended that the capacitors be placed on the same side of the board as the device. Ideally there
should be two bypass caps 0.1 µF and 0.001 µF in parallel. Run the power and return traces to the decoupling
capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power
chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum
thereby reducing the PCB trace inductance.
5. The use of a bulk capacitors distributed over the area of the power plane in the design is recommended to
improve the power supply stability particularly in the area of large current consumption devices. Typical values
range from 4.7 μF to 47 μF.
17.2 PCB Layer Strategy
1. 4-Layer PCB Example:
– Layer 1 component + signal side (short traces)
– Layer 2 ground plane
– Layer 3 power plane
– Layer 4 signal
Note: It is strongly recommended for all high-speed Ethernet LAN designs and minimum requirements to
meet most EMC, EMI, and EFT requirements.
Comprehensive PCB Layout Guidelines and Recommenda...
© 2022 Microchip T
echnology Inc.
and its subsidiaries
Manual
DS70005439B-page 68
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