Use the corresponding IOSET pins for the SPI interface signals in the SAM / PIC32C families for the
highest speeds possible.
• SQI peripheral modules have maximum input clock restrictions. Check the errata and data sheet for limitations.
•
At higher speeds ≥ 15 MHz use termination resistors on all high-speed output driver side signals. (See the
design example below, and Impedance Matching.)
Abbreviated General High-Speed Signal Layout Guidelines
1. Ensure the clock and high-speed signal traces have an unbroken reference ground plane with no gaps or
voids beneath them.
2. Copper pour all voids on signal layers with signal ground.
3. Minimize the use of vias throughout the design on high-speed signals. Vias add capacitance and impedance
changes at frequency to signal traces that lead to reflections and radiated EMI.
4. Use the 3-width rule to provide enough trace separation to avoid cross talk problems.
Note: See Complete PCB Layout Guidelines in the back of this document.
Figure 11-3. SPI and SQI External EEPROM/SRAM/FLASH Design Diagram
#WP
#HOLD
VCC
GND
SI
SCLK
SO
#CS
AT25160B
16Kb SPI EEPROM
23K640
64Kb SPI SRAM
MCU
SDO - MOSI
SCK
33
33
NOTE:
See appropriate MCU power
bypassing circuit configuration
illustrations in section 2.2
CS#
I/O
SDIx - MISO
I/O
#HOLD
VCC
GND
SI
SCLK
SO
#CS
33
CS#
VDD - VDDIO
VSS - GND
VDD
VDD
10k
10k
VCC
GND
SI/SIO0
MOSI/DATA0 - SQID0
#CS - SQICS0
MISO/DATA1 – SQID1
DATA2 – SQID2
DATA3 – SQID3
QSCK - SQICLK
SCLK
SO/SIO1
RESET#/HOLD#/SIO3
WP#/SIO2
#CE
33
33
33
33
33
33
33
33
33
33
5
6
1
2
3
7
VDD
4
8
1
2
3
4
5
6
7
8
4
33
1
2
5
6
7
8
SST26VF020A
2Mb SQI Flash
10k
VDD
Serial Data Corruption Errors
© 2022 Microchip T
echnology Inc.
and its subsidiaries
Manual
DS70005439B-page 37
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