Problem 38: Why will the CAN not connect?
11.7.1 CAN FD Silicon Configuration Requirements
• The maximum data rate error for CAN or CAN FD is ≤ 1%.
•
At least one CAN device must have a fixed CAN bit rate configured. If more than one CAN device has a fixed
CAN bit rate configured, it must be the same bit rate for each of the fixed CAN bit rate devices on the network.
• Each CAN node ID must be unique in the CAN network.
• The CAN data rate is determined by: the following:
– CAN Time quantum (i.e. TQ) = ((Data Baud Rate Prescalar + 1) / FCAN)
Note: The FCAN is the CAN module input clock frequency (Recommend 20 MHz, 40 MHz, or 80 MHz).
– Bit Period = (TQ * ((SYNC + (TSEG1 + 1) + (TSEG2 +1 )))
– CAN Bit Rate = (1 / (((BRP + 1)) / FCAN) * (SYNC + (TSEG1 + 1) + (TSEG2 + 1))))
OR Bit Rate = 1 / Bit Period
– 1% Error ≥ [(Bit Rate – User Desired bit rate) / Desired bit rate] * 100
Figure 11-12. CAN Nominal Bit Times Diagram
CAN PHASE SEGMENT RESTRICTION RULES
1.
(Prop Seg + Phase Seg1) ≥ Phase Seg2.
2. 8 ≤ (Sync (i.e. SJW) + Prop Seg + Phase Seg1+ Phase Seg2) ≤ 40.
3. Sync (i.e. SJW) ≤ Phase Seg 2.
Table 11-6. CAN FD Bit Time Registers
CAN FD SEGMENTS SAM & PIC32C PIC32MK
SYNC SEGMENT DBTP.DSJW
≥
NBTP.DSJW CFD1DBTCFG.SJW
≥
CFD1NBTCFG.SJW
PROP SEGMENT
DBTP.DTSEG1 NBTP.DTSEG1 CFD1DBTCFG.TSEG1 CFD1NBTCFG.TSEG1
PHASE SEG1
PHASE SEG2 DBTP.DTSEG2 NBTP.DTSEG2 CFD1DBTCFG.TSEG2 CFD1NBTCFG.TSEG2
Notes:
1.
The bit rate configured for the CAN FD data phase through the SAM/PIC32C [DBTP Reg] or the PIC32MK
[CFD1DBTCFG] must be higher or equal to the corresponding bit rate configured for the arbitration phase
through the SAM/PIC32C [NBTP Reg] or the PIC32MK [CFD1NBTCFG Reg].
2. The maximum CAN data rate error percentage must also consider the clock source inaccuracy + Jitter % error.
3. Check all of the above for proper configuration for the actual data rate versus the expected data rate and %
error.
Serial Data Corruption Errors
©
2022 Microchip Technology Inc.
and its subsidiaries
Manual
DS70005439B-page 48
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