Digital noise and current are generally much larger than that of the analog circuitry. As a result, choose a
layout strategy where the analog ground current has a separate and not additive digital ground current and
noise as depicted above. Use ground isolation barriers to steer and contain digital noise/current away from the
analog circuitry
. Remember that high frequency noise will seek the path of least inductance which is generally
the shortest distance on a ground plane. Most analog control signals from the digital domain are low and
medium speed so routing over ground voids in those instances is acceptable. In cases where high speed
signals from digital to analog domain is required, such as the audio codec Host clock, do not route over ground
voids. Instead, use an isolation barrier bridge as shown in the 1st example as well as a termination resistor at
the clock source of ~50 Ohms.
5. Do not run sensitive analog signals in parallel over or near fast digital transit signals. If necessary, then insure
they cross at right angles to minimize the capacitive cross section of the traces.
6. The lengths of traces carrying high-speed digital signals or clocks should be minimized. High-speed digital
signals and clocks are often the strongest noise sources. The longer these traces are, the more opportunities
there will be to couple energy away from these traces. Remember loop area is generally more important than
trace length. Make sure that there is a good high-frequency current return path very near each trace.
7. The lengths of traces attached directly to the connectors (I/O traces) must be minimized. Traces attached
directly to the connectors are likely paths for EMC, EMI, and EFT energy to be coupled on or off the board.
The use of TVS and ferrite beads and/or common mode chokes as required are recommended on all external
connector I/O pins. Refer to schematic recommended design protection examples.
8. In general, it is a good PCB design rule to not run any traces in between any surface mount pads (resistors,
capacitors, ferrite beads, etc).
9. PCB traces must be designed with the proper width for the amount of current they are expected to supply. The
use of mini planes in a local area on either the top or bottom layers will ensure the proper current supply.
10. All component leads to any power plane or ground plane should be as short as possible. The best solutions
are plane connection vias inside the surface mount pads. When using vias outside the surface mount pads,
pad-to-via connections must be less than 5 – 10 mils in length. Trace connections must be as wide as possible
to lower inductance. This will include any power ferrite beads feeding power planes, fuses feeding power
planes, and so on.
11. Signals with high-frequency content should not be routed beneath components used for board I/O. Traces
routed under a component can capacitive or inductively couple energy to that component.
12. All connectors when possible should be located on one edge or on one corner of a board. Connectors
represent the most efficient EMC/EMI antenna parts in most designs. Locating them on the same edge of the
board makes it much easier to control the common-mode voltage that may drive one connector relative to
another.
Comprehensive PCB Layout Guidelines and Recommenda...
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Manual
DS70005439B-page 65
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