697
D.DDWR, DP.DDWR
1
10
3
4
6
6
7
8
10.2 D.DDWR, DP.DDWR
Function
(1) In multiple CPU system, data stored in a device specified by host CPU ( ) or later is stored by the number of write points
specified by ( +1) into a device specified by another CPU (n) ( ) or later.
(2) Whether to complete the D(P).DDWR instruction normally can be checked by the completion device ( +0) and
completion status display device ( +1).
(a) Completion device ( +0)
Turns on at END processing in the scan where the instruction has been completed, and turns off at the next END
processing.
(b) Completion status display device ( +1)
This device turns on/off depending on the status upon completion of the instruction.
• Normal completion: Off
• Error completion: Turns on at END processing in the scan where the instruction has been completed, and turns
off at the next END processing (At error completion, an error code is stored at control data ( +0): Completion
status)).
(3) The number of blocks used for the instruction depends on the number of write points (refer to Page 686, Section 10.1).
Number of blocks used for the instruction
(4) The instruction will be completed abnormally when there are no empty blocks in the multiple CPU high speed
transmission area.
Set the number of blocks used for the instruction at special registers (SD796 to SD799), and use the special relays
(SM796 to SM799) as an interlock prevent error completion (refer to Page 687, Section 10.1).
Number of write points
specified by the instruction
D(P).DDWR
instruction
1 to 4 1
5 to 20 2
21 to 36 3
37 to 52 4
53 to 68 5
69 to 84 6
85 to 100 7
S2
D2 D1
Start device number of the
storage location for write data
S2
Number of write points
S1 +1
Host CPU
(CPU that requests writing)
Another CPU n
(CPU to be read)
Start device number of the storage
location where write data has stored
D1
D2
D2
D2
D2
S1
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