JTAG CoreSight 10 Interface
T
he below tablelists the JTAG CoreSight 10 pins description. For further details, please refer toJTAG CoreSight 10 Interface.
Pin Signal
Name
Voltage
Domain
Description
1 VTREF A The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target.
If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω.
2 TMS A The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller
inactive when not in use.
3 GND NA Ground.
4 TCK A The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target.
5 GND NA Ground.
6 TDO A The Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is
typically pulled HIGH on the target.
7 KEY (NC) NA This pin must not be present on the target connector.
8 TDI A The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target.
9 GND NA Ground.
10 nSRST A The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is
typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.
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