DDR4 DRAM Memory Interface
The below table lists the DDR4 DRAM pins description. For further details, please refer toDDR4 SODIMM Memory
.
Pin Name Description Pin Name Description
A0–A16 SDRAM address bus SCL I2C serial bus clock for SPD/TS
BA0, BA1 SDRAM bank select SDA I2C serial bus data line for SPD/TS
BG0, BG1 SDRAM bank group select SA0–SA2 I2C slave address select for SPD/TS
RAS_na SDRAM row address strobe PARITY SDRAM parity input
CAS_nb SDRAM column address strobe VDD SDRAM I/O & core power supply
WE_nc SDRAM write enable VPP SDRAM activating power supply
CS0_n, CS1_n CS2_n, CS3_n Rank Select Lines C0, C1 Chip ID lines for 3DS components
CKE0, CKE1 SDRAM clock enable lines VREFCA SDRAM command/address reference supply
ODT0, ODT1 SDRAM on-die termination control lines VSS Power supply return (ground)
ACT_n SDRAM activate VDDSPD Serial SPD/TS positive power supply
DQ0–DQ63 DIMM memory data bus ALERT_n SDRAM ALERT_n
CB0–CB7 DIMM ECC check bits
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