T2080
POR & Override
CPLD Register
CPLD
cfg_xxx
switch
Figure 20. DIP switch definition
Table 11 shows how POR configuration is done through switches.
Table 11. POR configuration through switches
Switch Signal name Pin name Signal meaning Setting
SW1[1:8] cfg_rcw_src[0:7] IFC_AD[8:15] Reset Configuration word source.
For details, see
T2080 Integrated
Multicore Communications
Processor Family Reference
Manual
(document T2080RM)
NOR boot: 00010011_1
NAND boot: 10000010_1
SPI boot: 00100010_1
SD boot: 00100000_0
SW2[1] cfg_rcw_src[8] IFC_CLE Reset Configuration word source For details, see
T2080 Integrated
Multicore Communications
Processor Family Reference
Manual
(document T2080RM)
SW2[2] cfg_ifc_te IFC_TE IFC external transceiver enable
polarity select
0: IFC drives logic 1 for
TE assertion
1: IFC drives logic 0 for
TE assertion
SW2[3] cfg_pll_config_sel
_b
IFC_A18 Reserved Reserved
SW2[4] cfg_por_ainit IFC_A19 Reserved Reserved
SW2[5:6] cfg_svr[0:1] IFC_A[16:17] Reserved Reserved
SW2[7] cfg_dram_type IFC_A21 DRAM type selection
1: DDR3L (1.35 V)
SW2[8] cfg_rsp_dis IFC_AVD Reserved Reserved
SW3[1] cfg_eng_use0 IFC_WE0 Sys_clock selection
1: Single sys_clk is selected
Table continues on the next page...
NXP Semiconductors
Architecture
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 28 / 44
To Next Page
Loading...
