12-2 Modbus Communication
AC10 Inverter
12.4 Frame structure:
ASCII mode
Byte Function
1
7
0/1
1/2
Start Bit (Low Level)
Data Bit
Parity Check Bit (None for this bit in case of no checking. Otherwise 1 bit)
Stop Bit (1 bit in case of checking, otherwise 2 bits)
RTU mode
Byte Function
1
8
0/1
1/2
Start Bit (Low Level)
Data Bit
Parity Check Bit (None for this bit in case of no checking. Otherwise 1 bit)
Stop Bit (1 bit in case of checking, otherwise 2 bits)
12.5 Error Check
12.5.1 ASCII mode
Longitudinal Redundancy Check (LRC): It is performed on the ASCII message field contents
excluding the ‘colon’ character that begins the message, and excluding the CRLF pair at the
end of the message.
The LRC is calculated by adding together successive 8–bit bytes of the message, discarding
any carries, and then two’s complementing the result.
A procedure for generating an LRC is:
1. Add all bytes in the message, excluding the starting ‘colon’ and ending CRLF. Add them into
an 8–bit field, so that carries will be discarded.
2. Subtract the final field value from FF hex (all 1’s), to produce the ones–complement.
3. Add 1 to produce the twos–complement.
12.5.2 RTU Mode
Cyclical Redundancy Check (CRC): The CRC field is two bytes, containing a 16–bit binary
value.
The CRC is started by first preloading a 16–bit register to all 1’s. Then a process begins of
applying successive 8–bit bytes of the message to the current contents of the register. Only the
eight bits of data in each character are used for generating the CRC. Start and stop bits, and
the parity bit, do not apply to the CRC.
A procedure for generating a CRC-16 is:
1. Load a 16–bit register with FFFF hex (all 1’s). Call this the CRC register.
2. Exclusive OR the first 8–bit byte of the message with the high–order byte of the 16–bit CRC
register, putting the result in the CRC register.
3. Shift the CRC register one bit to the right (toward the LSB), zero–filling the MSB. Extract and
examine the LSB.
4. (If the LSB was 0): Repeat Step 3 (another shift).
(If the LSB was 1): Exclusive OR the CRC register with the polynomial value A001 hex (1010
0000 0000 0001).
5. Repeat Steps 3 and 4 until 8 shifts have been performed. When this is done, a complete 8–
bit byte will have been processed.
When the CRC is appended to the message, the low-order byte is appended first, followed by
the high-order byte.
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