Rockwell Automation Publication 2080-UM002L-EN-E - November 2021 137
Chapter 8 Use the High-Speed Counter and Programmable Limit Switch
used in the control program to identify that the overflow variable caused the
HSC interrupt. If the control program needs to perform any specific control
action based on the overflow, this bit is used as conditional logic.
This bit can be cleared (0) by the control program and is also cleared by the
HSC sub-system whenever these conditions are detected:
• Low Preset Interrupt executes
• High Preset Interrupt executes
• Underflow Interrupt executes
The Underflow Interrupt status bit is set (1) when the HSC accumulator counts
through the underflow value and the HSC interrupt is triggered. This bit can
be used in the control program to identify that the underflow condition caused
the HSC interrupt. If the control program needs to perform any specific
control action based on the underflow, this bit is used as conditional logic.
This bit can be cleared (0) by the control program and is also cleared by the
HSC sub-system whenever these conditions are detected:
• Low Preset Interrupt occurs
• High Preset Interrupt occurs
• Overflow Interrupt occurs
The High Preset Interrupt status bit is set (1) when the HSC accumulator
reaches the high preset value and the HSC interrupt is triggered. This bit can
be used in the control program to identify that the high preset condition
caused the HSC interrupt. If the control program needs to perform any
specific control action based on the high preset, this bit is used as conditional
logic.
This bit can be cleared (0) by the control program and is also cleared by the
HSC sub-system whenever these conditions are detected:
• Low Preset Interrupt occurs
• Underflow Interrupt occurs
• Overflow Interrupt occurs
The Low Preset Interrupt status bit is set (1) when the HSC accumulator
reaches the low preset value and the HSC interrupt has been triggered. This bit
Underflow Interrupt (HSCSTS.UFCauseInter)
Description Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (HSCAPP.HSCMode) on page 127.
User Program Access
HSCSTS.UFCauseInter bit 2…9 read/write
High Preset Interrupt (HSCSTS.HPCauseInter)
Description Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (HSCAPP.HSCMode) on page 127.
User Program Access
HSCSTS.HPCauseInter bit 0…9 read/write
Low Preset Interrupt (HSCSTS.LPCauseInter)
Description Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (HSCAPP.HSCMode) on page 127.
User Program Access
HSCSTS.LPCauseInter bit 2…9 read/write
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