WRITE GATE
6.1.2
A write sequence
is
initiated when Write Gate
is
activated which causes the
Read/Write LSI (IC 6H, pin 26) to apply
+
12
Volts to the center tap
of
the
selected head. Concurrently, data
is
sent to the Read/Write LSI, pins
15
and
16.
WRITE
DATA
PROCESSING
6.1.3
DifferentiaI MFM write
data
is
received from the controller by the Read/Write
LSI and changed to digital pulse data. Depending on whether plus
or
minus
data
is
to be written, the Read/Write LSI (which controls the amount
of
cur-
rent to be written) activates either pin 7
or
8
of
the preamp LSI (IC 3H). When
writing to the inner heads
(2
and
3),
Write current
is
reduced to lessen the
problems
of
pulse crowding.
PRECOMPENSATION
6.1.4
TABLE
3:
Precompensation
Pattern
Precompensation
is
recommended
on
cylinders
128
through 306 in order to
achieve optimum performance. The optimum amount
of
precompensation
is
12
nsec.
for both early and late bits.
Table
3 below indicates the bit patterns
and the direction to be compensated. An X denotes a "don't care" state.
PREVIOUS SENDING
NEXT TIMING
X
0
1 1
WRITE DATA LATE
X 1
1
0
WRITE DATA EARLY
1
0 0
0
WRITE CLOCK LATE
0 0
0
1 WRITE CLOCK EARLy
ALL·OTHER PATTERNS NOMINAL
ST212
PRODUCT
MANUAL/Rev.
B
23
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