Cycle and response times
7.6 Sample calculations
• Response times plus I/O delay:
–
Case 1: An output channel of the digital output module is set when a signal is received
at the digital input. This produces a response time of:
Response time = 40 ms + 4.8 ms = 44.8 ms.
–
Case 2: An analog value is fetched, and an analog value is output. This produces a
response time of:
Longest response time = 40 ms + 176 ms + 3.3 ms = 219.3 ms.
7.6.3 Calculation example for the interrupt response time of the CPU 315T-2 DP
Structure
You have assembled an S7-300, consisting of one CPU 315T-2 DP and four digital modules
in the central rack. One of the digital input modules is an SM 321; DI 16 x 24 VDC; with
process/diagnostic interrupt function.
In the parameter assignment of the CPU and the SM, you have only enabled the process
interrupt. You do not require time-driven processing, diagnostics and error handling. You
have set a cycle load caused by communication of 20%.
You have set an input delay of 0.5 ms for the digital input module.
No activities are necessary at the cycle checkpoint.
Calculation
The process interrupt response time for the example results from the following times:
• Process interrupt response time of CPU 315T-2 DP: approx. 0.7 ms
• Extension by communication according to the formula:
200 μs + 1000 μs x 20 % = 400 μs = 0.4 ms
• Process interrupt response time of SM 321; DI 16 x 24 VDC:
– Internal interrupt preparation time: 0.25 ms
– Input delay: 0.5 ms
• Since the signal modules are plugged into the central rack, the DP cycle time on the
PROFIBUS DP is not relevant.
The process interrupt response time results from the sum of the listed times:
Process interrupt response time = 0.7 ms + 0.4 ms + 0.25 ms + 0.5 ms = approx. 1.85 ms.
This calculated process interrupt response time is the time from a signal being applied
across the digital input to the first statement in OB 40.
S7-300 CPU Data: CPU 315T-2 DP
7-20 Manual, 12/2005, A5E00427933-02
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