Overview of All Actions
S7-GRAPH for S7-300/400 Programming Sequential Control Systems
C79000-G7076-C526-01
13-19
Action Explanation
Event In-
struc-
tion
Address Location Address
range
S0 TR T
<time>
X As soon as the step is deactivated (leaves state)
the timer stops. Timer bit (status of the timer) and
timer value are reset to 0.
x = no.
of timer
L1: Timers in actions linked with interlocks leaving state
L1 TL T
<time>
X As soon as the interlock condition is satisfied when
the step is no longer satisfied (leaves state) while
the step is active or if the interlock condition is not
satisfied when the step becomes active, the timer
starts. For the specified time, the timer bit (status of
the timer) is set to 1, when the time elapses, it is
reset to 0.
x = no.
of timer
L1 TD T
<time>
X As soon as the interlock condition is satisfied when
the step is no longer satisfied (leaves state) while
the step is active or if the interlock condition is not
satisfied when the step becomes active, the timer
starts. For the specified time, the timer bit (status of
the timer) is set to 0, when the time elapses, it is set
to 1.
x = no.
of timer
L1 TR T
<time>
X As soon as the interlock condition is satisfied when
the step is no longer satisfied (leaves state) while
the step is active or if the interlock condition is not
satisfied when the step becomes active, the timer
stops. Timer bit (status of the timer) and timer value
are reset to 0.
x = no.
of timer
L0: Timers in actions linked with interlocks entering state
L0 TL T
<time>
X As soon as the interlock condition is satisfied when
the step is active (enters state), the timer starts. For
the specified time, the timer bit (status of the timer)
is set to 1, when the time elapses, it is reset to 0.
x = no.
of timer
L0 TD T
<time>
X As soon as the interlock condition is satisfied when
the step is active (enters state), the timer starts. For
the specified time, the timer bit (status of the timer)
is set to 0, when the time elapses, it is set to 1.
x = no.
of timer
L0 TR T
<time>
X As soon as the interlock condition is satisfied when
the step is active (enters state), the timer stops.
Timer bit (status of the timer) and timer value are
reset to 0.
x = no.
of timer
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