Mobility and Logistics, Traffic Solutions
Sopers Lane, Poole, Dorset, BH17 7ER
Security classification
property name.
Page
17 of 73
Version 008
Status
Released
Last Editor Nathan Fearnhead
Date
16/06/2017
Document Name Configuration Control
Document No.
667/CC/32750/000
Copyright © Mobility 2017. All Rights Reserved. Mobility is a division of Siemens Plc
3.2.5 CPU PCB
The CPU PCB will be configured with the appropriate firmware for the variant of Outercase
specified. The CPU PCB in completely contained within a sub division of the ST750ELV
Backplane Rack Assembly, and is mounted vertically. The CPU PCB is connected to several
other PCBs, within the ST750ELV Backplane Rack Assembly and to external units.
A 34 way ribbon cable from the manual control panel is connected into the central 34 way socket
at the rear of the CPU PCB, connector X2.
The 16 way Molex plug at the bottom rear of the CPU PCB, connector X4, is connected to PL7 on
the Backplane Board.
Communications between the CPU PCB and Intelligent Detector Backplanes, detailed in
paragraph 6.7, are carried out via a high speed serial link, over RJ45/Cat 5 cable. Connection of
this serial link from the processor is carried as follows:
- PL1 on the PHS processor daughter board (part of the CPU PCB) is connected to SK10
on the Backplane Board.
- PL4 on the PHS processor daughter board is connected to SK11 on the Backplane Board.
- PL2 on the PHS processor daughter board is connected to serial IN socket on the first
Intelligent Detector Backplane. Refer to paragraph 3.7 below for details on Intelligent
Detector Backplane.
Note: An Input Output Expansion Kit can be specified, which also utilises the Fast Serial
Link. Please refer to section 3.8 for information on Input Output Expansion Kit.
Figure 6
Phase and
Phase return
Terminal Blocks
Audible and
Relay output
Terminal Blocks
Detector Power
Terminal Blocks
Digital input
Terminals
Blocks