Sony HCD-BC150 - Page 157

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HCD-BC150/BC250
Pin No. Pin Name I/O Description
142 RD20 I DRAM data input
143 RD19 I DISCEXT signal
144 RD18 — Not used (open)
145 DVSS — Terminal Ground
146 RD17 I DRAM data input
147 RD16 I DRAM data input
148 ABCK O Audio bit clock (Not used)
149 ALRCK I Audio left/right channnel clock (Not used)
150 DVDD3 — Power Supply (+3.3V)
151 ACLK I Audio DAC master clock (Not used)
152 MC-DATA I Microphone serial input (Not used)
153 SPDIF O SPDIF output
154 ASDATA0 I Auio serial data (Not used)
155 ASDATA1 I Auio serial data (Not used)
156 ASDATA2 I Auio serial data (Not used)
157 ASDATA3 I Auio serial data (Not used)
158 ASDATA4 I Auio serial data (Not used)
159 BACVDDC — 3.3V power pin for VIDEO DAC circuitry
160 VREF I Bandgap referrence voltage (Not used)
161 FS O Full scale adjustment
162 YUV/CIN O Video data output bit0/Compensation capacitor (Not used)
163 DACVSSC — Terminal Ground
164 YUV/C O CHROMA signal output to VIDEO AMP (IC201)
165 DACVDDB — Power Supply (+3.3V)
166 YUV2/Y O Y signal output to VIDEO AMP (IC201)
167 DACVSSB O Terminal Ground
168 YU3/CVBS O VIDEO signal output to VIDEO AMP (IC201)
169 DACVDDA — Power Supply (+3.3V)
170 YUV4/G O G signal output to VIDEO AMP (IC201)
171 DACVSSA — Terminal Ground
172 YUV5/B O B signal output to VIDEO AMP (IC201)
173 YUV6/R O R signal output to VIDEO AMP (IC201)
174 IEC I Microcontroller ICE mode enable (Not used)
175 BKANK I/O Video blank area,active low
176 VSYN I/O Vertical sync (Not used)
177 YUV7 I/O Video data output (Not used)
178 DVSS — Terminal Ground
179 HSYN I/O Horizontal sync (Not used)
180 SPMCLK I Audio DAC master clock of SPDIF input (Not used)
181 SPDATA I IPSEL signal input from SYSTEM CONTROLLER (IC509)
182 DVDD2 — Power Supply (+2.5V)
183 SPLRCK I Audio left/right channnel clock of SPDIF input (Not used)
184 SPBCK I Not used (open)
185 DVDD3 — Power Supply (+3.3V)
186 XTALO O Oscillator output signal
187 XTALI I Oscillator input signal
188 PRST I MTRST signal input from SYSTEM CONTROLLER (IC509)