VIDEO SYSTEM CONTROLLER
IC3610 (2/3)
HDMI BUFFER
IC8305
AUDIO MUTE REQ
D3502
D3512
HDMI_ERROR
BUFFER
IC3518
13TX 5VPWR1
TX_5VPWR1
82HDSEL_POWER
HDSEL_POWER
15TX 5VPWR2
TX_5VPWR2
53
46
7
SI*NAL PATH
AUDIO (DI*ITAL)
: VIDEO
CN3505
HDMI
ASSI*NABLE
(INPUT ONLY)
IN 2
CN3506
HDMI
ASSI*NABLE
(INPUT ONLY)
IN 1
CN8308
HDMI IN 6
R0X0+
R0X0–
R0X1+
R0X1–
R0X2+
R0X2–
R0XC+
R0XC–
130
129
7
9
132
131
4
6
134
133
1
3
128
127
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA2+
DATA2–
CLOCK+
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLU* DET
18
CEC
13
12
16
15
HDMI RECEIVER
IC3511 (2/2)
40
39
139
138
7
9
141
140
4
6
143
142
1
3
137
136
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA2+
DATA2–
CLOCK+
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLU* DET
18
CEC
13
12
16
15
44
19
43
11 2
111
7
9
11 4
11 3
4
6
11 6
11 5
1
3
11 0
109
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA2+
DATA2–
CLOCK+
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLU* DET
18
CEC
CEC
F-HDMI +3.3V
13
12
16
15
DSDA0
32
DSCL0
31
INT
22
RESET#
21
RX INT
48
16
RX RST
31
19
19
38
42
R3X0+
R3X0–
R3X1+
R3X1–
R3X2+
R3X2–
R3XC+
R3XC–
DSDA3
DSCL3
HPD3
41
R3PWR5V
R2X0+
R2X0–
R2X1+
R2X1–
R2X2+
R2X2–
R2XC+
R2XC–
DSDA2
DSCL2
HPD2
37
R2PWR5V
34
33
40
39
46
45
4
AP
AN
BP
BN
CP
CN
DP
DN
WP
WN
XP
XN
YP
YN
ZP
ZN
3
23
24
20
21
16
17
13
14
LEVEL SHIFT
IC8306
HDMI OUTPUT SELECTOR
IC3111
C8
de_a
A8
hsync_a
B8
vsync_a
A9
clk_a
out_o<0> – out_o<35>
36
HPD0
30
R0PWR5V
29
+3.3V
RE*ULATOR
IC8307
in_a<0> – in_a<35>
A7, C7, A6, B6, C6, A5, C5, C4, B4, A4, B3, A3,
C2, C1, D1, E1, D3, E2, E3, F3, F1, *1, *2, H1,
*3, H3, -2, -3, -1, K1, L1, M1, K3, L2, L3, M3
B12
de_b
A12
hsync_b
A11
vsync_b
C9
clk_b
in_b<2> – in_b<11>,
in_b<14> – in_b<23>,
in_b<26> – in_b<35>
A14, B15, C12, C13, D14, C15, C16, D15, D16, E16,
F14, *14, F16, *16, H16, -16, H15, H14, -14, K14,
L16, M16, L14, M15, M14, N14, N16, P15, P16, R15
11
D–VIDEO BUS2
RX_VSYNC
RX_HSYNC
RX_DE
RX_ODCK[1]
Q[0] – Q[35]
12
D–VIDEO BUS3
FLI_VSYNC
FLI_HSYNC
FLI_DE
FLI_ODCK
D[2] – D[11],
D[14] – D[23],
D[26] – D[35]
36
30
P1, P2, R1, T2, R3, T3, P4, T4, N4, P5, N6, N7, R5,
T5, P6, T6, P7, N8, T8, P8, N9, N10, P10, N11, P9, T10,
T11, R11, P11, P12, N12, P13, R13, T13, R14, T14
T9clk_o<1>
T7clk_o<0>
N3vsync_o
N2hsync_o
N1de_o
13
D–VIDEO BUS4
S_VSYNC
S_HSYNC
S_DE
S_ODCK[1]
S_ODCK[2]
S[0] – S[35]
p_sel
D12
81
REPEAT_PATH_SEL
p_th
D13
83
HSYNC_TH
reset
D9
80
HDSEL_RESET
*PIO3/
MUTEOUT
107
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