Sony STR-DA5500ES - Block Diagram - ETHERNET, XM Section (2;2)

STR-DA5500ES
STR-DA5500ES
3131
5-10. BLOCK DIAGRAM - ETHERNET, XM Section (2/2) -
MM_CLK
M1
MM_CLK_N
M2
SD-RAM
IC8002
CONNECTED MEDIA PROCESSOR
IC8013 (2/2)
FLASH ROM
IC8001
MM_DATA0 – MM_DATA15
I/O0 – I/O7
I/O0 – I/O7
I/O0 – I/O7
MM_DATA00 –
MM_DATA15
MM_ADDR00 – MM_ADDR12
MM_ADDR00 – MM_ADDR12
MM_CKE
J2
MM_BA0
R4
MM_BA1
P4
MM_CS0_N
L3
MM_RAS_N
L1
MM_CAS_N
M4
MM_WE_N
N3
MM_DQM0
K2
MM_DQM1
J4
MM_DQS0
J1
45
46
44
26
27
24
23
22
21
20
47
16
G1
CLK
/CLK
CKE
BA0
BA1
CS
RAS
CAS
WE
LDM
UDM
LDQS
UDQS
CLK
/CLK
CKE
BA0
BA1
CS
RAS
CAS
WE
LDM
UDM
LDQS
UDQS
51
8
16
17
18
9
RE
CLE
ALE
WE
CE
R/B
7
MM_DQS1
PCI_AD24 –
PCI_AD31
PCI_AD02
Y26
PCI_AD01
W23
PCI_AD00
Y23
PCI_C/BE2_N
M26
PCI_C/BE1_N
R23
XIO_SEL0
AB26
AC20
XIO_ACK
PCI_GNT_A_N
D25
AC23
XIO_SEL3
BOOT_MODE07
AD26
AC18
CLOCK04
A7
XIO_SEL2
SD-RAM
IC8004
MM_DATA16 – MM_DATA31
MM_CLK MM_CLK_N MM_CKE MM_BA0 MM_BA1 MM_CS0_N MM_RAS_N MM_CAS_N MM_WE_N
MM_CLK
MM_CLK_N
MM_CKE
MM_BA0
MM_BA1
MM_CS0_N
MM_RAS_N
MM_CAS_N
MM_WE_N
MM_DQM2
V3
MM_DQM3
U2
MM_DQS2
Y1
45
46
44
26
27
24
23
22
21
20
47
16
V1 51
MM_DQS3
MM_DATA16 –
MM_DATA31
DQ0 – DQ15
I/O0 – I/O7
A0 – A12
DQ16 – DQ31
A0 – A12
MM_ADDR00 –
MM_ADDR12
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
WE
RE
AD02
ALE
CLE
CE
RB
WE
ALE
RE
WE
CLE
ALE
CLE
RE
R/B
CE
WE
RE
CLE
ALE
AD02
29 – 32,
41 – 44
PARALLEL BUS/I2C
BUS CONVERTER
IC8201
15
14
12
11
16
A1
A0
RD
WR
INT
INT
CE
RESET
13
17
1 – 8
I/O0 – I/O7
ANALOG
SWITCH
IC8251
PARALLEL/SERIAL
CONVERTER
IC8204
12
5
28
27
26
BAUDOUT
RCLK
A0
A1
A2
RD1
WR1
19
16
D0 – D7
2 – 3,
43 – 47
11
CS2_N
MR(RESET)
INTRPT
30
SDA
19
18
SCL
XIN
14
XOUT
15
PNX_SDA
PNX_SCL
77
RESET SWITCH
Q8201 – 8203
RESET
76
35
SIN
7
SOUT
8
NET-UART_NET/M
NET-UART_M/NET
NET-UART_SEL
71
SELECT SWITCH
Q8003
X8200
3.6864MHz
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(Page 30)
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