ST STM32WB Series Programming Manual

Core peripherals PM0214
204/262 PM0214 Rev 9
4.2.9 MPU region attribute and size register (MPU_RASR)
Address offset: 0x10
Reset value: 0x0000 0000
Required privilege: Privileged
The MPU_RASR register defines the region size and memory attributes of the MPU region
specified by the MPU_RNR, and enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes
• The least significant halfword holds the region size and the region and subregion
enable bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved XN
Reserved
AP[2:0] Reserved TEX[2:0] S C B
rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
SRD[7:0] Reserved SIZE
EN ABLE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:29 Reserved, forced by hardware to 0.
Bit 28 XN: Instruction access disable bit:
0: Instruction fetches enabled
1: Instruction fetches disabled.
Bit 27 Reserved, forced by hardware to 0.
Bits 26:24 AP[2:0]: Access permission
For information about access permission, see Section 4: Core peripherals
For a description of AP bits encoding refer to
Table 41 on page 196.
Bits 23:22 Reserved, forced by hardware to 0.
Bits 21:19 TEX[2:0]: memory attribute
For a description of TEX bits encoding refer to
Table 39 on page 195
Bit 18 S: Shareable memory attribute
For a description of S bits encoding refer to
Table 39 on page 195
Bit 17 C: memory attribute
Bit 16 B: memory attribute

ST STM32WB Series Specifications

General

Brand	ST
Model	STM32WB Series
Category	Computer Hardware
Language	English