PM0214 Rev 9 185/262
PM0214 The STM32 Cortex-M4 instruction set
261
3.11.5 ISB
Instruction synchronization barrier.
Syntax
ISB{cond}
Where: ‘cond’ is an optional condition code, see Conditional execution on page 65.
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so
that all instructions following the ISB are fetched from cache or memory again, after the ISB
instruction is completed.
Condition flags
This instruction does not change the flags.
Examples
ISB ; Instruction Synchronisation Barrier
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