ST STM32WB Series Programming Manual

PM0214 Rev 9 195/262
PM0214 Core peripherals
261
4.2.1 MPU access permission attributes
This section describes the MPU access permission attributes. The access permission bits,
TEX, C, B, S, AP, and XN, of the MPU_RASR register, control access to the corresponding
memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 39 shows the encodings for the TEX, C, B, and S access permission bits.
Table 40 shows the cache policy for memory attribute encodings with a TEX value is in the
range 4-7.
Table 39. TEX, C, B, and S encoding
TEX C B S Memory type Shareability Other attributes
b000
0
0x
(1)
1. THe MPU ignores the value fo this bit.
Strongly-ordered Shareable -
1 x
(1)
Device Shareable -
1
0
0
Normal
Not shareable
Outer and inner write-through. No
write allocate.
1 Shareable
1
0
Normal
Not shareable
Outer and inner write-back. No write
allocate.
1 Shareable
b001
0
00
Normal
Not shareable
Outer and inner noncacheable.
- 1 Shareable
1 x
(1)
Reserved encoding -
1
0 x
(1)
Implementation defined attributes. -
1
0
Normal
Not shareable
Outer and inner write-back. Write
and read allocate.
1 Shareable
b010
0
0 x
(1)
Device Not shareable Nonshared Device.
1 x
(1)
Reserved encoding -
1x
(1)
x
(1)
Reserved encoding -
b1BB A A
0
Normal
Not shareable
Cached memory
(2)
, BB = outer
policy, AA = inner policy.
2. See Table 40 for the encoding of the AA and BB bits.
1 Shareable
Table 40. Cache policy for memory attribute encoding
Encoding, AA or BB Corresponding cache policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate

ST STM32WB Series Specifications

General

Brand	ST
Model	STM32WB Series
Category	Computer Hardware
Language	English