The STM32 Cortex-M4 instruction set PM0214
88/262 PM0214 Rev 9
Examples
CLZ R4,R9
CLZNE R2,R3
3.5.5 CMP and CMN
Compare and Compare Negative.
Syntax
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
Where:
• ‘cond’ is an optional condition code (see Conditional execution on page 65).
• ‘Rn’ is the register holding the first operand.
• ‘Operand2’ is a flexible second operand (see Flexible second operand on page 60) for
details of the options.
Operation
These instructions compare the value in a register with operand2. They update the condition
flags on the result, but do not write the result to a register.
The CMP instruction subtracts the value of operand2 from the value in Rn. This is the same
as a SUBS instruction, except that the result is discarded.
The CMN instruction adds the value of operand2 to the value in Rn. This is the same as an
ADDS instruction, except that the result is discarded.
Restrictions
In these instructions:
• Do not use PC.
• Operand2 must not be SP.
Condition flags
These instructions update the N, Z, C and V flags according to the result.
Examples
CMP R2, R9
CMN R0, #6400
CMPGT SP, R7, LSL #2
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