ST STM32WB Series Programming Manual

Core peripherals PM0214
194/262 PM0214 Rev 9
When memory regions overlap, a memory access is affected by the attributes of the region
with the highest number. For example, the attributes for region 7 take precedence over the
attributes of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory
map, but is accessible from privileged software only.
The Cortex-M4 MPU memory map is unified. This means instruction accesses and data
accesses have same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor
generates a memory management fault. This causes a fault exception, and might cause
termination of the process in an OS environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on
the process to be executed. Typically, an embedded OS uses the MPU for memory
protection.
Configuration of MPU regions is based on memory types, see Section 2.2.1: Memory
regions, types and attributes on page 29.
Table 38 shows the possible MPU region attributes.
Table 38. Memory attributes summary
Memory type Shareability Other attributes Description
Strongly-ordered - -
All accesses to Strongly-ordered
memory occur in program order. All
Strongly-ordered regions are assumed
to be shared.
Device
Shared -
Memory-mapped peripherals that
several processors share.
Non-shared -
Memory-mapped peripherals that only a
single processor uses.
Normal
Shared
Non-cacheable
Write-through Cacheable
Write-back Cacheable
Normal memory that is shared between
several processors.
Non-shared
Non-cacheable
Write-through Cacheable
Write-back Cacheable
Normal memory that only a single
processor uses.

ST STM32WB Series Specifications

General

Brand	ST
Model	STM32WB Series
Category	Computer Hardware
Language	English