Core peripherals PM0214
228/262 PM0214 Rev 9
4.4.5 Application interrupt and reset control register (AIRCR)
Address offset: 0x0C
Reset value: 0xFA05 0000
Required privilege: Privileged
The AIRCR provides priority grouping control for the exception model, endian status for data
accesses, and reset control of the system.
To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the
processor ignores the write.
Binary point
The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields in
the Interrupt Priority Registers into separate group priority and subpriority fields. Table 51
shows how the PRIGROUP value controls this split. If you implement fewer than 8 priority
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEYSTAT[15:0](read)/ VECTKEY[15:0](write)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
ENDIANESS
Reserved
PRIGROUP
Reserved
SYS
RESET
REQ
VECT
CLR
ACTIVE
VECT
RESET
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Bits 31:16 VECTKEYSTAT/ VECTKEY Register key
Reads as 0xFA05
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
Bit 15 ENDIANESS Data endianness bit
Reads as 0.
0: Little-endian
Bits 14:11 Reserved, must be kept cleared
Bits 10:8 PRIGROUP: Interrupt priority grouping field
This field determines the split of group priority from subpriority, see Binary point on page 228.
Bits 7:3 Reserved, must be kept cleared
Bit 2 SYSRESETREQ System reset request
This is intended to force a large system reset of all major components except for debug.
This bit reads as 0.
0: No system reset request
1: Asserts a signal to the outer system that requests a reset.
Bit 1 VECTCLRACTIVE
Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to
this bit, otherwise behavior is unpredictable.
Bit 0 VECTRESET
Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to
this bit, otherwise behavior is unpredictable.
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