ST STM32WB Series

The Cortex-M4 processor PM0214
22/262 PM0214 Rev 9
Interrupt program status register
The IPSR contains the exception type number of the current Interrupt Service Routine
(ISR). See the register summary in Table 3 on page 18 for its attributes.
The bit assignment is:
Execution program status register
The EPSR contains the Thumb state bit, and the execution state bits for either the:
• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
multiple instruction.
See the register summary in Table 3 on page 18 for the EPSR attributes. The bit assignment
is:
Table 6. IPSR bit definitions
Bits Description
Bits 31:9 Reserved
Bits 8:0 ISR_NUMBER:
This is the number of the current exception:
0: Thread mode
1: Reserved
2: NMI
3: Hard fault
4: Memory management fault
5: Bus fault
6: Usage fault
7: Reserved
....
10: Reserved
11: SVCall
12: Reserved for Debug
13: Reserved
14: PendSV
15: SysTick
16: IRQ0
(1)
....
....
255: IRQ240
(1)
see Exception types on page 37 for more information.
1. Depends on product. Refer to reference manual/datasheet of relevant STM32 product for related
information.