PM0214 Rev 9 73/262
PM0214 The STM32 Cortex-M4 instruction set
261
3.4.3 LDR and STR, register offset
Load and Store with register offset.
Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
Where:
• ‘op’ is either LDR (load register) or STR (store register).
• ‘type’ is one of the following:
B: Unsigned byte, zero extends to 32 bits on loads.
SB: Signed byte, sign extends to 32 bits (LDR only).
H: Unsigned halfword, zero extends to 32 bits on loads.
SH: Signed halfword, sign extends to 32 bits (LDR only).
—: Omit, for word.
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• ‘Rt’ is the register to load or store.
• ‘Rn’ is the register on which the memory address is based.
• ‘Rm’ is a register containing a value to be used as the offset.
• ‘LSL #n’ is an optional shift, with n in the range 0 to 3.
Operation
LDR instructions load a register with a value from memory. STR instructions store a register
value into memory. The memory address to load from or store to is at an offset from the
register Rn. The offset is specified by the Rm register and can be shifted left by up to 3 bits
using LSL. The value to load or store can be a byte, halfword, or word. For load instructions,
bytes and halfwords can either be signed or unsigned (see Address alignment on page 65).
Restrictions
In these instructions:
• Rn must not be PC.
• Rm must be neither SP nor PC.
• Rt can be SP only for word loads and word stores.
• Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address.
• If the instruction is conditional, it must be the last instruction in the IT block.
Condition flags
These instructions do not change the flags.
Examples
STR R0, [R5, R1]; store value of R0 into an address equal to
; sum of R5 and R1
LDRSB R0, [R5, R1, LSL #1]; read byte value from an address equal to
; sum of R5 and two times R1, sign extended it
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