The STM32 Cortex-M4 instruction set PM0214
178/262 PM0214 Rev 9
3.10.28 VSTR
Floating-point Store.
Syntax
VSTR{cond}{.32} Sd, [Rn{, #imm}]
VSTR{cond}{.64} Dd, [Rn{, #imm}]
Where:
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• ‘32, 64’ are the optional data size specifiers.
• ‘Sd’ is the source register for a singleword store.
• ‘Dd’ is the source register for a doubleword store.
• ‘Rn’ is the base register. The SP can be used.
• ‘imm’ is the + or - immediate offset used to form the address. Values are multiples of 4
in the range 0-1020. imm can be omitted, meaning an offset of +0.
Operation
This instruction stores a single extension register to memory, using an address from an Arm
core register, with an optional offset, defined in imm.
Restrictions
The restrictions are the use of PC for Rn is deprecated.
Condition flags
These instructions do not change the flags.
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