ST STM32WB Series Programming Manual

Core peripherals PM0214
226/262 PM0214 Rev 9
Bit 28 PENDSVSET: PendSV set-pending bit.
Write:
0: No effect
1: Change PendSV exception state to pending.
Read:
0: PendSV exception is not pending
1: PendSV exception is pending
Writing 1 to this bit is the only way to set the PendSV exception state to pending.
Bit 27 PENDSVCLR: PendSV clear-pending bit. This bit is write-only. On a read, value is unknown.
0: No effect
1: Removes the pending state from the PendSV exception.
Bit 26 PENDSTSET: SysTick exception set-pending bit.
Write:
0: No effect
1: Change SysTick exception state to pending
Read:
0: SysTick exception is not pending
1: SysTick exception is pending
Bit 25 PENDSTCLR: SysTick exception clear-pending bit. Write-only. On a read, value is unknown.
0: No effect
1: Removes the pending state from the SysTick exception.
Bit 24 Reserved, must be kept cleared.
Bit 23 This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
Bit 22 ISRPENDING: Interrupt pending flag, excluding NMI and Faults.
0: Interrupt not pending
1: Interrupt pending
Bits 21:19 Reserved, must be kept cleared.
Bits 18:12 VECTPENDING: Pending vector. Indicates the exception number of the highest priority
pending enabled exception.
0: No pending exceptions
Other values: The exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK
registers, but not any effect of the PRIMASK register.
Bit 11 RETTOBASE: Return to base level. Indicates whether there are preempted active
exceptions:
0: There are preempted active exceptions to execute
1: There are no active exceptions, or the currently-executing exception is the only active
exception.
Bits 10:9 Reserved
Bits 8:0
VECTACTIVE Active vector. Contains the active exception number:
0: Thread mode
Other values: The exception number
(1)
of the currently active exception.
Note: Subtract 16 from this value to obtain CMSIS IRQ number required to index into the
Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or Priority Registers,
see Table 6 on page 22.
1. This is the same value as IPSR bits[8:0], see Interrupt program status register on page 22.

ST STM32WB Series Specifications

General

Brand	ST
Model	STM32WB Series
Category	Computer Hardware
Language	English